diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-30 18:39:53 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-02 19:33:11 +0100 |
| commit | 6372a0eef14dd97f2743d7d1820e2446cc997bd2 (patch) | |
| tree | c11de01ba9aeef406cafde2018041bb2c339730b /src | |
| parent | 4291e8b6ca0cc62a2d1945422b9eb3a2c9318dac (diff) | |
nb/intel/i945/early_init.c: Use "IS_ENABLED(CONFIG_ ....)"
Change-Id: I230b5425ac9e916a5ee10a49eeaf5d6d44fd49e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17192
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 4373167693..5d1a0c28c3 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -90,9 +90,9 @@ static void i945m_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC - printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); -#endif + + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) + printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); } static void i945_detect_chipset(void) @@ -139,9 +139,9 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM - printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); -#endif + + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); } static void i945_setup_bars(void) |