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authorMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2022-11-03 15:38:23 -0500
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2022-11-05 12:13:50 +0000
commit624aa04ed617d3326aad4f005efc60da33da9693 (patch)
tree52209765d8e398f4c2cdfc04e499839582d8e26f /src
parentcf886b54efddeb0efe497659ad9710d3ed4097bf (diff)
mb/google/guybrush: rename baseboard GPIO table getter for clarity
Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since the GPIO table comes from the baseboard and is overridden by a separate table from the variant. Drop the __weak qualifier as this function is not overridden. This is similar to the change made for skyrim in CB:67809 Change-Id: I14c79fad04f18d874ce6ff7e572bb237445db8b1 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/guybrush/romstage.c2
-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/gpio.c2
-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/guybrush/romstage.c b/src/mainboard/google/guybrush/romstage.c
index 23e7853a05..0b7649b87a 100644
--- a/src/mainboard/google/guybrush/romstage.c
+++ b/src/mainboard/google/guybrush/romstage.c
@@ -9,7 +9,7 @@ void mb_pre_fspm(void)
const struct soc_amd_gpio *base_gpios, *override_gpios;
/* Initialize PCIe reset. */
- base_gpios = variant_pcie_gpio_table(&base_num_gpios);
+ base_gpios = baseboard_pcie_gpio_table(&base_num_gpios);
override_gpios = variant_pcie_override_gpio_table(&override_num_gpios);
gpio_configure_pads_with_override(base_gpios, base_num_gpios,
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index 8554c4c671..1ee70dae33 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -286,7 +286,7 @@ static const struct soc_amd_gpio pcie_gpio_table[] = {
PAD_NFO(GPIO_26, PCIE_RST_L, HIGH),
};
-const struct soc_amd_gpio *__weak variant_pcie_gpio_table(size_t *size)
+const struct soc_amd_gpio *baseboard_pcie_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(pcie_gpio_table);
return pcie_gpio_table;
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
index bf694438bb..9a57c41eff 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
@@ -30,7 +30,7 @@ const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size);
/* This function provides GPIO settings before PCIe enumeration. */
-const struct soc_amd_gpio *variant_pcie_gpio_table(size_t *size);
+const struct soc_amd_gpio *baseboard_pcie_gpio_table(size_t *size);
/* This function provides GPIO settings for eSPI bus. */
const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size);