remove trailing whitespace

Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
author: Stefan Reinauer <reinauer@chromium.org> 2011-10-31 12:56:45 -0700
committer: Patrick Georgi <patrick@georgi-clan.de> 2011-11-01 19:07:45 +0100
commit: 5ff7c13e858a31addf1558731a12cf6c753b576d (patch)
tree: 82ed6cf7b45f3a86c2c43ab87383355ed6012d6c /src
parent: 784544b934d67dc85ccfcf33e04ff148045836ad (diff)
250 files changed, 816 insertions, 816 deletions
diff --git a/src/arch/x86/include/arch/romcc_io.h b/src/arch/x86/include/arch/romcc_io.h
index 79ea26550e..b0c8f65f46 100644
--- a/src/arch/x86/include/arch/romcc_io.h
+++ b/src/arch/x86/include/arch/romcc_io.h
@@ -3,7 +3,7 @@
 
 #include <stdint.h>
 
-// arch/io.h is pulled in in many places but it could 
+// arch/io.h is pulled in in many places but it could
 // also be pulled in here for all romcc/romstage code.
 // #include <arch/io.h>
 
diff --git a/src/console/die.c b/src/console/die.c
index 8c97f89b27..395ab75538 100644
--- a/src/console/die.c
+++ b/src/console/die.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2003 Eric Biederman
  *
  * This program is free software; you can redistribute it and/or
diff --git a/src/console/post.c b/src/console/post.c
index 7fc9d6fc6e..08336a28e9 100644
--- a/src/console/post.c
+++ b/src/console/post.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2003 Eric Biederman
  *
  * This program is free software; you can redistribute it and/or
diff --git a/src/cpu/amd/agesa/apic_timer.c b/src/cpu/amd/agesa/apic_timer.c
index ec6ddd5473..ec6ddd5473 100755..100644
--- a/src/cpu/amd/agesa/apic_timer.c
+++ b/src/cpu/amd/agesa/apic_timer.c
diff --git a/src/cpu/amd/agesa/family10/chip.h b/src/cpu/amd/agesa/family10/chip.h
index d5a749b3c6..d5a749b3c6 100755..100644
--- a/src/cpu/amd/agesa/family10/chip.h
+++ b/src/cpu/amd/agesa/family10/chip.h
diff --git a/src/cpu/amd/agesa/family10/chip_name.c b/src/cpu/amd/agesa/family10/chip_name.c
index d99769c92a..d99769c92a 100755..100644
--- a/src/cpu/amd/agesa/family10/chip_name.c
+++ b/src/cpu/amd/agesa/family10/chip_name.c
diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c
index 8c1cfaddfc..8c1cfaddfc 100755..100644
--- a/src/cpu/amd/agesa/family10/model_10_init.c
+++ b/src/cpu/amd/agesa/family10/model_10_init.c
diff --git a/src/cpu/amd/agesa/family12/chip.h b/src/cpu/amd/agesa/family12/chip.h
index f63a87f5d9..f63a87f5d9 100755..100644
--- a/src/cpu/amd/agesa/family12/chip.h
+++ b/src/cpu/amd/agesa/family12/chip.h
diff --git a/src/cpu/amd/agesa/family12/chip_name.c b/src/cpu/amd/agesa/family12/chip_name.c
index 5de72c73ea..5de72c73ea 100755..100644
--- a/src/cpu/amd/agesa/family12/chip_name.c
+++ b/src/cpu/amd/agesa/family12/chip_name.c
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index d74b33308b..d74b33308b 100755..100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index 90b83e5bf9..6df1032d98 100644
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -91,7 +91,7 @@ static const struct {
 
 	{ BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL,
 	  0x00000000, 1 << (35-32),
-	  0x00000000, 1 << (35-32) },	/* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() )  */  
+	  0x00000000, 1 << (35-32) },	/* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() )  */
 
 	{ OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL,
 	  0x00000004, 0x00000000,
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index 6cbd096f67..6be054c87f 100644
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -17,84 +17,84 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 /*
- * This file initializes the CPU cores for voltage and frequency settings 
+ * This file initializes the CPU cores for voltage and frequency settings
  * in the different power states.
  */
 /*
 
 checklist (functions are in this file if no source file named)
-Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 
+Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010
 
 2.4.2.6 Requirements for p-states
 
 1.- F3x[84:80] According to table 100 : prep_fid_change
 
-2.- COF/VID : 
-     2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply 
-               fixPsNbVidBeforeWR(...) 
+2.- COF/VID :
+     2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply
+               fixPsNbVidBeforeWR(...)
      2.4.2.9.1 Step 8 enable_fid_change
-               We do this for all nodes, I don't understand BKDG 100% on 
-               whether this is or isn't meant by "on the local 
+               We do this for all nodes, I don't understand BKDG 100% on
+               whether this is or isn't meant by "on the local
                processor". Must be OK.
      2.4.2.9.1 Steps 9-10 (repeat 1-7 and reset) romstage.c/init_cpus ?
      2.4.2.9.1 Steps 11-12 init_fidvid_stage2
-     2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect, 
-               needs specific circuitry. 
+     2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect,
+               needs specific circuitry.
 
 3.-  2.4.2.7 dualPlaneOnly(dev)
 
 4.-  2.4.2.8 applyBoostFIDOffset(dev)
 
-5.-  enableNbPState1(dev) 
+5.-  enableNbPState1(dev)
 
-6.- 2.4.1.7 
+6.- 2.4.1.7
     a) UpdateSinglePlaneNbVid()
     b) setVSRamp(), called from  prep_fid_change
     c) prep_fid_change
-    d) improperly, for lack of voltage regulator details?, 
-        F3xA0[PsiVidEn] in defaults.h 
+    d) improperly, for lack of voltage regulator details?,
+        F3xA0[PsiVidEn] in defaults.h
         F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change)
 
-7.- TODO (Core Performance Boost is only available in revision E cpus, and we 
-          don't seem to support those yet, at least they don't have any 
+7.- TODO (Core Performance Boost is only available in revision E cpus, and we
+          don't seem to support those yet, at least they don't have any
           constant in amddefs.h )
 
-8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required 
-    by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required 
-    if the warm reset is issued by coreboot to update NbFid. So it is required 
-    or not ? How can I tell who issued warm reset ? 
-    Coreboot transitions to P0 instead, which is not recommended, and does 
+8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required
+    by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required
+    if the warm reset is issued by coreboot to update NbFid. So it is required
+    or not ? How can I tell who issued warm reset ?
+    Coreboot transitions to P0 instead, which is not recommended, and does
     not follow 2.4.2.15.2 to do so.
 
-9.- TODO Requires information on current delivery capability 
-    (depends on mainboard and maybe power supply ?). One might use a config 
+9.- TODO Requires information on current delivery capability
+    (depends on mainboard and maybe power supply ?). One might use a config
     option with the maximum number of Ampers that the board can deliver to CPU.
 
 10.- [Multiprocessor] TODO 2.4.2.12
-     [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2, 
-     but not sure this is what is meant by "Determine the valid set of 
-     P-states based on enabled P-states indicated 
+     [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2,
+     but not sure this is what is meant by "Determine the valid set of
+     P-states based on enabled P-states indicated
      in MSRC001_00[68:64][PstateEn]" in 2.4.2.6-10
 
 11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway)
 
-12.- generate ACPI for p-states. FIXME 
+12.- generate ACPI for p-states. FIXME
      Needs more assesment. There's some kind of fixed support that
      does not seem to depend on CPU revision or actual MSRC001_00[68:64]
-     as BKDG apparently requires. 
+     as BKDG apparently requires.
      http://www.coreboot.org/ACPI#CPU_Power_Management
      At least for Tilapia board:
      src/mainboard/<vendor>/<model>/acpi_tables.c  write_acpi_tables(...) calls
-      acpi_add_ssdt_pstates(...) 
+      acpi_add_ssdt_pstates(...)
      in /src/northbridge/amd/amdfam10/amdfam10_acpi.c
      which apparently copies them from static info in
-     src/mainboard/<vendor>/<model>/acpi/cpstate.asl 
-     
+     src/mainboard/<vendor>/<model>/acpi/cpstate.asl
+
 "must also be completed"
 
 a.-  PllLockTime set in ruleset in defaults.h
-     BKDG says set it "If MSRC001_00[68:64][CpuFid] is different between 
-     any two enabled P-states", but since it does not say "only if" 
+     BKDG says set it "If MSRC001_00[68:64][CpuFid] is different between
+     any two enabled P-states", but since it does not say "only if"
      I guess it is safe to do it always.
 
 b.-  prep_fid_change(...)
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index ce5c810821..ae5429d05d 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -265,7 +265,7 @@ static void init_ecc_memory(unsigned node_id)
 
 	/* See if we scrubbing should be enabled */
 	enable_scrubbing = 1;
-	if( get_option(&enable_scrubbing, "hw_scrubber") < 0 ) 
+	if( get_option(&enable_scrubbing, "hw_scrubber") < 0 )
 	{
 		enable_scrubbing = CONFIG_HW_SCRUBBER;
 	}
@@ -443,7 +443,7 @@ static inline void k8_errata(void)
 #endif
 	{
 		msr = rdmsr(NB_CFG_MSR);
-		
+
 #if CONFIG_K8_REV_F_SUPPORT == 0
 		if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
 			/* D0 later don't need it */
@@ -461,11 +461,11 @@ static inline void k8_errata(void)
 		 */
 		msr.lo |= 1 << 3;
 		/* Erratum 169 */
-		/* This supersedes erratum 131; 131 should not be applied with 169 
+		/* This supersedes erratum 131; 131 should not be applied with 169
 		 * We also need to set some bits in the northbridge, handled in src/northbridge/amdk8/
 		 */
 		msr.hi |= 1;
-		
+
 		wrmsr(NB_CFG_MSR, msr);
 	}
 	/* Erratum 122 */
diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c
index ff61a30f9a..473766c8a4 100644
--- a/src/cpu/amd/model_gx2/cpubug.c
+++ b/src/cpu/amd/model_gx2/cpubug.c
@@ -280,7 +280,7 @@ static void bug118339(void)
 
 	/* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled
 	 * As per Todd Roberts in PBz1094 and PBz1095
-	 * Moved from CPUREG to CPUBUG per Tom Sylla 
+	 * Moved from CPUREG to CPUBUG per Tom Sylla
 	 */
 	msrnum =  0x04C000042;		/*  GLCP SETMCTL Register */
 	msr = rdmsr(msrnum);
diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c
index 6e7de84c6a..bad98b51bf 100644
--- a/src/cpu/amd/model_lx/cpureginit.c
+++ b/src/cpu/amd/model_lx/cpureginit.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
  * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
@@ -83,7 +83,7 @@ static const struct delay_controls {
  * hardware is not an exact science. And, finally, if an FS2 (JTAG debugger)
  * is hooked up, then just don't do anything. This code was written by a master
  * of the Dark Arts at AMD and should not be modified in any way.
- * 
+ *
  * [1] (http://www.thefreedictionary.com/juju)
  *
  * @param dimm0 The SMBus address of DIMM 0 (mainboard dependent).
diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c
index 6569338a2f..9c6e98e14c 100644
--- a/src/cpu/amd/model_lx/msrinit.c
+++ b/src/cpu/amd/model_lx/msrinit.c
@@ -45,7 +45,7 @@ static const msrinit_t msr_table[] =
 	 * of this extended memory will be to host the coreboot_ram stage at RAMBASE,
 	 * currently 1Mb.
 	 * These registers will be set to their correct value by the Northbridge init code.
-	 * 
+	 *
 	 * WARNING: if coreboot_ram could not be loaded, these registers are probably
 	 * incorrectly set here. You may comment the following two lines and set RAMBASE
 	 * to 0x4000 to revert to the previous behavior for LX-boards.
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index fc22ea4adf..fc22ea4adf 100755..100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c
index 4d7357c93a..0c15b1560c 100644
--- a/src/devices/oprom/x86.c
+++ b/src/devices/oprom/x86.c
@@ -36,7 +36,7 @@ void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
 		u32 esi, u32 edi) __attribute__((regparm(0))) =
 						(void *)&__realmode_call;
 
-void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
+void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,
 		u32 esi, u32 edi) __attribute__((regparm(0))) =
 						(void *)&__realmode_interrupt;
 
@@ -361,7 +361,7 @@ void do_vsmbios(void)
 	printk(BIOS_DEBUG, "Calling VSA module...\n");
 
 	/* ECX gets SMM, EDX gets SYSMEM */
-	realmode_call(VSA2_ENTRY_POINT, 0x0, 0x0, MSR_GLIU0_SMM, 
+	realmode_call(VSA2_ENTRY_POINT, 0x0, 0x0, MSR_GLIU0_SMM,
 			MSR_GLIU0_SYSMEM, 0x0, 0x0);
 
 	printk(BIOS_DEBUG, "... VSA module returned.\n");
diff --git a/src/devices/oprom/x86_asm.S b/src/devices/oprom/x86_asm.S
index 57c5338914..488bfa6b91 100644
--- a/src/devices/oprom/x86_asm.S
+++ b/src/devices/oprom/x86_asm.S
@@ -255,7 +255,7 @@ __realmode_interrupt = RELOCATED(.)
 	data32 ljmp	$0, $RELOCATED(1f)
 1:
 
-	/* put the stack at the end of page zero.  That way we can easily 
+	/* put the stack at the end of page zero.  That way we can easily
 	 * share it between real mode and protected mode, because %esp and
 	 * %ss:%sp point to the same memory.
 	 */
diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c
index 26a7caff0d..747b343cc8 100644
--- a/src/drivers/ati/ragexl/xlinit.c
+++ b/src/drivers/ati/ragexl/xlinit.c
@@ -22,7 +22,7 @@
 #include <device/pci_ops.h>
 
 // FIXME BTEXT console within coreboot has been obsoleted
-// and will go away. The BTEXT code in this file should be 
+// and will go away. The BTEXT code in this file should be
 // fixed to export a framebuffer console through the coreboot
 // table (and possibly make it available for bootsplash use)
 // Hence do only remove this if you fix the code.
diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c
index c89d4f08de..416b5ae6d9 100644
--- a/src/drivers/dec/21143/21143.c
+++ b/src/drivers/dec/21143/21143.c
@@ -30,7 +30,7 @@ static void dec_21143_enable(device_t dev)
 
 	// The resource allocator should do this. If not, it needs to be fixed
 	// differently.
-#if 0 
+#if 0
 	/* Command and status configuration (offset 0x04) */
 	pci_write_config32(dev, 0x04, 0x02800107);
 	printk(BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n",
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
index 235c52c654..3480654cfe 100644
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -29,7 +29,7 @@
 		CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION)
 
 #define OXPCIE_DEVICE \
-	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0) 
+	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0)
 
 void oxford_init(void)
 {
@@ -57,7 +57,7 @@ void oxford_init(void)
 
 	/* Memory window for the OXPCIe952 card */
 	// XXX is the calculation of base and limit corect?
-	pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE, 
+	pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE,
 			((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) |
 			((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00)));
 
@@ -66,7 +66,7 @@ void oxford_init(void)
 	reg16 |= PCI_COMMAND_MEMORY;
 	pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
 
-	// FIXME Add a timeout or this will hang forever if 
+	// FIXME Add a timeout or this will hang forever if
 	// no device is in the slot.
 	u32 id = 0;
 	while ((id == 0) || (id == 0xffffffff))
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index f1c12b38e8..a72da69bd5 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -12,7 +12,7 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
@@ -20,32 +20,32 @@
 
 /**
  * @file post_codes.h
- * 
+ *
  * This aims to be a central point for POST codes used throughout coreboot.
  * All POST codes should be declared here as macros, and post_code() should
  * be used with the macros instead of hardcoded values. This allows us to
  * quicly reference POST codes when nothing is working
- * 
+ *
  * The format for a POST code macro is
  * #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED
  * Lets's keep it at POST_* instead of POST_CODE_*
- * 
+ *
  * This file is also included by early assembly files. Only use #define s;
  * no function prototypes allowed here
- * 
+ *
  * DOCUMENTATION:
- * Please document any and all post codes using Doxygen style comments. We 
+ * Please document any and all post codes using Doxygen style comments. We
  * want to be able to generate a verbose enough documentation that is useful
  * during debugging. Failure to do so will result in your patch being rejected
  * without any explanation or effort on part of the maintainers.
- * 
+ *
  */
 #ifndef POST_CODES_H
 #define POST_CODES_H
 
 /**
  * \brief  Entry into 'crt0.s'. reset code jumps to here
- * 
+ *
  * First instruction that gets executed after the reset vector jumps.
  * This indicates that the reset vector points to the correct code segment.
  */
@@ -53,7 +53,7 @@
 
 /**
  * \brief Entry into protected mode
- * 
+ *
  * Preparing to enter protected mode. This is POSTed right before changing to
  * protected mode.
  */
@@ -61,14 +61,14 @@
 
 /**
  * \brief Start copying coreboot to RAM with decompression if compressed
- * 
+ *
  * POSTed before ramstage is about to be loaded into memory
  */
 #define POST_PREPARE_RAMSTAGE 			0x11
 
 /**
  * \brief Copy/decompression finished; jumping to RAM
- * 
+ *
  * This is called after ramstage is loaded in memory, and before
  * the code jumps there. This represents the end of romstage.
  */
@@ -77,14 +77,14 @@
 
 /**
  * \brief Entry into c_start
- * 
+ *
  * c_start.S is the first code executing in ramstage.
  */
 #define POST_ENTRY_C_START			0x13
 
 /**
  * \brief Entry into coreboot in hardwaremain (RAM)
- * 
+ *
  * This is the first call in hardwaremain.c. If this code is POSTed, then
  * ramstage has succesfully loaded and started executing.
  */
@@ -92,14 +92,14 @@
 
 /**
  * \brief Console is initialized
- * 
+ *
  * The console is initialized and is ready for usage
  */
 #define POST_CONSOLE_READY			0x39
 
 /**
  * \brief Console boot message succeeded
- * 
+ *
  * First console message has been succesfully sent through the console backend
  * driver.
  */
@@ -107,28 +107,28 @@
 
 /**
  * \brief Devices have been enumerated
- * 
+ *
  * Bus scan, and device enumeration has completed.
  */
 #define POST_DEVICE_ENUMERATION_COMPLETE	0x66
 
 /**
  * \brief Devices have been configured
- * 
+ *
  * Device confgration has completed.
  */
 #define POST_DEVICE_CONFIGURATION_COMPLETE	0x88
 
 /**
  * \brief Devices have been enabled
- * 
+ *
  * Devices have been enabled.
  */
 #define POST_DEVICES_ENABLED			0x89
 
 /**
  * \brief Entry into elf boot
- * 
+ *
  * This POST code is called right before invoking jmp_to_elf_entry()
  * jmp_to_elf_entry() invokes the payload, and should never return
  */
@@ -136,7 +136,7 @@
 
 /**
  * \brief Jumping to payload
- * 
+ *
  * Called right before jumping to a payload. If the boot sequence stops with
  * this code, chances are the payload freezes.
  */
@@ -144,16 +144,16 @@
 
 /**
  * \brief Not supposed to get here
- * 
+ *
  * A function that should not have returned, returned
- * 
+ *
  * Check the console output for details.
  */
 #define POST_DEAD_CODE				0xee
 
 /**
  * \brief Pre call to hardwaremain()
- * 
+ *
  * POSTed right before hardwaremain is called from c_start.S
  * TODO: Change this code to a lower number
  */
@@ -161,9 +161,9 @@
 
 /**
  * \brief Elfload fail or die() called
- * 
+ *
  * Coreboot was not able to load the payload, no payload was detected
- * or die() was called. 
+ * or die() was called.
  * \n
  * If this code appears before entering ramstage, then most likely
  * ramstage is corrupted, and reflashing of the ROM chip is needed.
@@ -182,7 +182,7 @@
  * They overlap with previous codes, and most are not even used
  * Some maiboards still require them, but they are deprecated. We want to consolidate
  * our own POST code structure with the codes above.
- * 
+ *
  * standard AMD post definitions for the AMD Geode
  */
 #define POST_Output_Port			(0x080)	/*	port to write post codes to*/
diff --git a/src/include/cpu/amd/amdfam12.h b/src/include/cpu/amd/amdfam12.h
index cabd532f2e..cabd532f2e 100755..100644
--- a/src/include/cpu/amd/amdfam12.h
+++ b/src/include/cpu/amd/amdfam12.h
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index a473d66c8f..c2de073a52 100644
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -22,7 +22,7 @@
 
 /*
  * Need two versions because ROMCC chokes on certain clobbers:
- * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: 
+ * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33:
  * 0x1559920 asm        Internal compiler error: lhs 1 regcm == 0
  */
 
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index e8bc195307..40926df602 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -23,7 +23,7 @@ typedef struct msr_struct
 	unsigned hi;
 } msr_t;
 
-typedef struct msrinit_struct 
+typedef struct msrinit_struct
 {
         unsigned index;
         msr_t msr;
diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c
index e79cb63346..75d51ffa83 100644
--- a/src/lib/uart8250mem.c
+++ b/src/lib/uart8250mem.c
@@ -120,7 +120,7 @@ u32 uart_mem_init(void)
 
 	if (dev) {
 		struct resource *res = find_resource(dev, 0x10);
-	
+
 		if (res) {
 			uart_bar = res->base + 0x1000; // for 1st UART
 			// uart_bar = res->base + 0x2000; // for 2nd UART
@@ -131,7 +131,7 @@ u32 uart_mem_init(void)
 #endif
 	uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART
 	// uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART
-	
+
 	div = 4000000 / uart_baud;
 #endif
 
diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c
index 6b75acf523..800ee52ae3 100644
--- a/src/lib/usbdebug.c
+++ b/src/lib/usbdebug.c
@@ -167,7 +167,7 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
 		bytes[i] = (hi >> (8*(i - 4))) & 0xff;
 }
 
-static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, 
+static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug,
 		unsigned devnum, unsigned endpoint, const char *bytes, int size)
 {
 	u32 pids, addr, ctrl;
@@ -234,7 +234,7 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum,
 
 int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size)
 {
-	return dbgp_bulk_read(dbg_info->ehci_debug, dbg_info->devnum, 
+	return dbgp_bulk_read(dbg_info->ehci_debug, dbg_info->devnum,
 			dbg_info->endpoint_in, data, size);
 }
 
@@ -373,7 +373,7 @@ int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *in
 	int playtimes = 3;
 
 	ehci_caps  = (struct ehci_caps *)ehci_bar;
-	ehci_regs  = (struct ehci_regs *)(ehci_bar + 
+	ehci_regs  = (struct ehci_regs *)(ehci_bar +
 			HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
 	ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset);
 	info->ehci_debug = (void *)0;
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
index 7dcdd96098..a72f96b4c3 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #include "agesawrapper.h"
 #include "amdlib.h"
 #include "BiosCallOuts.h"
@@ -58,11 +58,11 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
   {AGESA_GET_IDS_INIT_DATA,
    BiosGetIdsInitData
   },
-  
+
   {AGESA_HOOKBEFORE_DQS_TRAINING,
    BiosHookBeforeDQSTraining
   },
-  
+
   {AGESA_HOOKBEFORE_DRAM_INIT,
    BiosHookBeforeDramInit
   },
@@ -210,7 +210,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
        to the end of the allocated nodes list.
       */
-       
+
     }
     /* Find the node that best fits the requested buffer size */
     FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
@@ -260,7 +260,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
       /* If BestFitNode is the first buffer in the list, then update
          StartOfFreedNodes to reflect the new free node
-      */         
+      */
       if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
         BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
       } else {
@@ -345,10 +345,10 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       FreedNodePtr->NextNodeOffset = 0;
 
     } else {
-      /* Otherwise, add freed node to the start of the list 
-         Update NextNodeOffset and BufferSize to include the 
+      /* Otherwise, add freed node to the start of the list
+         Update NextNodeOffset and BufferSize to include the
          size of BIOS_BUFFER_NODE
-      */   
+      */
       AllocNodePtr->NextNodeOffset = FreedNodeOffset;
     }
     /* Update StartOfFreedNodes to the new first node */
@@ -356,7 +356,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   } else {
     /* Traverse list of freed nodes to find where the deallocated node
        should be place
-    */   
+    */
     NextNodeOffset = FreedNodeOffset;
     NextNodePtr = FreedNodePtr;
     while (AllocNodeOffset > NextNodeOffset) {
@@ -370,7 +370,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
     /* If deallocated node is adjacent to the next node,
        concatenate both nodes
-    */   
+    */
     if (NextNodeOffset == EndNodeOffset) {
       NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
       AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
@@ -384,7 +384,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
     }
     /* If deallocated node is adjacent to the previous node,
        concatenate both nodes
-    */   
+    */
     PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
     EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
     if (AllocNodeOffset == EndNodeOffset) {
@@ -448,10 +448,10 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   UINT8                 Value;
   UINTN               ResetType;
   AMD_CONFIG_PARAMS   *StdHeader;
-  
+
   ResetType = Data;
   StdHeader = ConfigPtr;
-    
+
   //
   // Perform the RESET based upon the ResetType. In case of
   // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
@@ -463,17 +463,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   case WARM_RESET_WHENEVER:
   case COLD_RESET_WHENEVER:
     break;
-    
+
   case WARM_RESET_IMMEDIATELY:
   case COLD_RESET_IMMEDIATELY:
       Value = 0x06;
       LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
     break;
-    
+
   default:
     break;
   }
-  
+
   Status = 0;
   return Status;
 }
@@ -506,10 +506,10 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   UINT8             Data8;
   UINT16            Data16;
   UINT8             TempData8;
-    
+
   FcnData = Data;
   MemData = ConfigPtr;
-  
+
   Status  = AGESA_SUCCESS;
   /* Get SB800 MMIO Base (AcpiMmioAddr) */
   WriteIo8 (0xCD6, 0x27);
@@ -520,14 +520,14 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   Data16  |= Data8;
   AcpiMmioAddr = (UINT32)Data16 << 16;
   GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-  
+
   Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
   Data8 &= ~BIT5;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-   
+
   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
@@ -546,7 +546,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   TempData8 &= 0x23;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-  
+
   switch(MemData->ParameterListPtr->DDR3Voltage){
     case VOLT1_35:
       Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
@@ -586,12 +586,12 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   AGESA_STATUS Status;
   UINTN                 FcnData;
   PCIe_SLOT_RESET_INFO  *ResetInfo;
-  
+
   UINT32  GpioMmioAddr;
   UINT32  AcpiMmioAddr;
   UINT8   Data8;
   UINT16  Data16;
-  
+
   FcnData   = Data;
   ResetInfo = ConfigPtr;
   // Get SB800 MMIO Base (AcpiMmioAddr)
@@ -611,13 +611,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 &= ~(UINT8)BIT6 ; 
+        Data8 &= ~(UINT8)BIT6 ;
         Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
@@ -634,7 +634,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
         Status = AGESA_SUCCESS;
         break;
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.h b/src/mainboard/amd/inagua/BiosCallOuts.h
index 2912ec6f51..4efe15fa4d 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.h
+++ b/src/mainboard/amd/inagua/BiosCallOuts.h
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #ifndef _BIOS_CALLOUT_H_
 #define _BIOS_CALLOUT_H_
 
@@ -45,7 +45,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 
 /* REQUIRED CALLOUTS
  * AGESA ADVANCED CALLOUTS - CPU
- */  
+ */
 AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c
index 1840afc552..4f000717fe 100644
--- a/src/mainboard/amd/inagua/PlatformGnbPcie.c
+++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c
@@ -56,7 +56,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-        }       
+        }
 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {
@@ -116,8 +116,8 @@ OemCustomizeInitEarly (
   //
   // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   //
-  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  + 
-                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 + 
+  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
+                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
                                          sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
 
   AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
@@ -125,10 +125,10 @@ OemCustomizeInitEarly (
   Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-    ASSERT(FALSE); 
+    ASSERT(FALSE);
     return Status;
   }
-  
+
   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
@@ -136,7 +136,7 @@ OemCustomizeInitEarly (
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
   BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
- 
+
   LibAmdMemFill (BrazosPcieComplexListPtr,
                    0,
                    sizeof (PCIe_COMPLEX_DESCRIPTOR),
@@ -146,7 +146,7 @@ OemCustomizeInitEarly (
                    0,
                    sizeof (PCIe_PORT_DESCRIPTOR) * 5,
                    &InitEarly->StdHeader);
-     
+
   LibAmdMemFill (BrazosPcieDdiPtr,
                    0,
                    sizeof (PCIe_DDI_DESCRIPTOR) * 2,
@@ -160,7 +160,7 @@ OemCustomizeInitEarly (
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 
-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; 
-  InitEarly->GnbConfig.PsppPolicy      = 0; 
+  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+  InitEarly->GnbConfig.PsppPolicy      = 0;
 }
 
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
index f35d8db723..b51089f7f6 100644
--- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
@@ -25,42 +25,42 @@
 #include "amdlib.h"
 
 //GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
@@ -68,5 +68,5 @@ VOID
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );
-  
+
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c
index 4c084e0aba..cc37ed24b0 100644
--- a/src/mainboard/amd/inagua/acpi_tables.c
+++ b/src/mainboard/amd/inagua/acpi_tables.c
@@ -62,18 +62,18 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
-  
+
   /* create all subtables for processors */
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
-  
+
   /* Write SB800 IOAPIC, only one */
   current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800,
              IO_APIC_ADDR, 0);
 
   current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
             current, 0, 0, 2, 0);
-  
+
   /* 0: mean bus 0--->ISA */
   /* 0: PIC 0 */
   /* 2: APIC 2 */
diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c
index cbdb23d5ed..df5cd1e9a9 100644
--- a/src/mainboard/amd/inagua/agesawrapper.c
+++ b/src/mainboard/amd/inagua/agesawrapper.c
@@ -21,7 +21,7 @@
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */
- 
+
 #include <stdint.h>
 #include <string.h>
 #include "agesawrapper.h"
@@ -52,8 +52,8 @@ VOID *AcpiSlit    = NULL;
 
 VOID *AcpiWheaMce = NULL;
 VOID *AcpiWheaCmc = NULL;
-VOID *AcpiAlib    = NULL; 
- 
+VOID *AcpiAlib    = NULL;
+
 
 /*----------------------------------------------------------------------------------------
  *                  T Y P E D E F S     A N D     S T R U C T U  R E S
@@ -64,17 +64,17 @@ VOID *AcpiAlib    = NULL;
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */
- 
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
- 
+
 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
-UINT32 
+UINT32
 agesawrapper_amdinitcpuio (
   VOID
   )
@@ -84,30 +84,30 @@ agesawrapper_amdinitcpuio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
-  
+
   /* Enable MMIO on AMD CPU Address Map Controller */
-  
+
   /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
   PciData = 0x00000B00;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
   PciData = 0x00000A03;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  
+
   /* Set TOM-DFFFFFFF to Node0 Link0. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
   PciData = 0x00DFFF00;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
   PciData = 0x00FFFF00 | 0x80;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
   PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
@@ -121,8 +121,8 @@ agesawrapper_amdinitcpuio (
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 }
- 
-UINT32 
+
+UINT32
 agesawrapper_amdinitmmio (
   VOID
   )
@@ -132,29 +132,29 @@ agesawrapper_amdinitmmio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
-  
+
   /*
    Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
    Address MSR register.
   */
   MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
   LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
-  
+
   /*
    Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
   */
   LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
   MsrReg = MsrReg | 0x0000400000000000;
   LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-  
+
   /* Set Ontario Link Data */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
   PciData = 0x01308002;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
 
   /* Set ROM cache onto WP to decrease post time */
   MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
@@ -166,7 +166,7 @@ agesawrapper_amdinitmmio (
   return (UINT32)Status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdinitreset (
   VOID
   )
@@ -174,7 +174,7 @@ agesawrapper_amdinitreset (
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
   AMD_RESET_PARAMS AmdResetParams;
-  
+
   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),
@@ -196,14 +196,14 @@ agesawrapper_amdinitreset (
   AmdParamStruct.StdHeader.ImageBasePtr = 0;
   AmdCreateStruct (&AmdParamStruct);
   AmdResetParams.HtConfig.Depth = 0;
-  
+
   status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
   if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
   AmdReleaseStruct (&AmdParamStruct);
   return (UINT32)status;
- }  
-  
-UINT32 
+ }
+
+UINT32
 agesawrapper_amdinitearly (
   VOID
   )
@@ -211,7 +211,7 @@ agesawrapper_amdinitearly (
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
   AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
-  
+
   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),
@@ -224,10 +224,10 @@ agesawrapper_amdinitearly (
   AmdParamStruct.StdHeader.Func = 0;
   AmdParamStruct.StdHeader.ImageBasePtr = 0;
   AmdCreateStruct (&AmdParamStruct);
-  
+
   AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
   OemCustomizeInitEarly (AmdEarlyParamsPtr);
-  
+
   status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
   if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
   AmdReleaseStruct (&AmdParamStruct);
@@ -235,7 +235,7 @@ agesawrapper_amdinitearly (
   return (UINT32)status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdinitpost (
   VOID
   )
@@ -277,7 +277,7 @@ agesawrapper_amdinitpost (
   return (UINT32)status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdinitenv (
   VOID
   )
@@ -304,7 +304,7 @@ agesawrapper_amdinitenv (
   /* Initialize Subordinate Bus Number and Secondary Bus Number
    * In platform BIOS this address is allocated by PCI enumeration code
      Modify D1F0x18
-   */  
+   */
   PciAddress.Address.Bus = 0;
   PciAddress.Address.Device = 1;
   PciAddress.Address.Function = 0;
@@ -407,17 +407,17 @@ agesawrapper_getlateinitptr (
   }
 }
 
-UINT32 
+UINT32
 agesawrapper_amdinitmid (
   VOID
   )
 {
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
-  
+
   /* Enable MMIO on AMD CPU Address Map Controller */
   agesawrapper_amdinitcpuio ();
-  
+
   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),
@@ -439,7 +439,7 @@ agesawrapper_amdinitmid (
   return (UINT32)status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdinitlate (
   VOID
   )
@@ -475,9 +475,9 @@ agesawrapper_amdinitlate (
   return (UINT32)Status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdlaterunaptask (
-  UINT32 Data, 
+  UINT32 Data,
   VOID *ConfigPtr
   )
 {
@@ -512,7 +512,7 @@ agesawrapper_amdlaterunaptask (
   return (UINT32)Status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdreadeventlog (
   VOID
   )
diff --git a/src/mainboard/amd/inagua/agesawrapper.h b/src/mainboard/amd/inagua/agesawrapper.h
index fd46dc6358..f6e6decad6 100644
--- a/src/mainboard/amd/inagua/agesawrapper.h
+++ b/src/mainboard/amd/inagua/agesawrapper.h
@@ -21,8 +21,8 @@
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */
- 
-  
+
+
 #ifndef _AGESAWRAPPER_H_
 #define _AGESAWRAPPER_H_
 
@@ -66,17 +66,17 @@ typedef struct {
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */
- 
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
- 
+
 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
- 
+
 //void brazos_platform_stage(void);
 UINT32 agesawrapper_amdinitreset (void);
 UINT32 agesawrapper_amdinitearly (void);
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index 686f7fa717..919f6be907 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 /**
  * @file
  *
@@ -57,13 +57,13 @@
 #define INSTALL_FT1_SOCKET_SUPPORT  TRUE
 #define INSTALL_AM3_SOCKET_SUPPORT  FALSE
 
-/* 
- * Agesa optional capabilities selection.  
+/*
+ * Agesa optional capabilities selection.
  * Uncomment and mark FALSE those features you wish to include in the build.
  * Comment out or mark TRUE those features you want to REMOVE from the build.
  */
 
-#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE    
+#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_12_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_14_SUPPORT       FALSE
 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT       TRUE
@@ -104,7 +104,7 @@
 //#define BLDOPT_REMOVE_HT_ASSIST         TRUE
 //#define BLDOPT_REMOVE_ATM_MODE          TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE  
+//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
 //#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
@@ -125,10 +125,10 @@
 #define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
 #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
 
-/* 
- * Agesa configuration values selection.  
+/*
+ * Agesa configuration values selection.
  * Uncomment and specify the value for the configuration options
- * needed by the system. 
+ * needed by the system.
  */
 
 /* The fixed MTRR values to be set after memory initialization. */
diff --git a/src/mainboard/amd/inagua/dimmSpd.c b/src/mainboard/amd/inagua/dimmSpd.c
index d6bf5b28e1..d82cb5d2c0 100644
--- a/src/mainboard/amd/inagua/dimmSpd.c
+++ b/src/mainboard/amd/inagua/dimmSpd.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"
@@ -51,7 +51,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
    UINT64 limit;
 
    address |= 1; // set read bit
-   
+
    __outbyte (iobase + 0, 0xFF);                // clear error status
    __outbyte (iobase + 1, 0x1F);                // clear error status
    __outbyte (iobase + 3, offset);              // offset in eeprom
@@ -108,7 +108,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
  *
  * readspd - Read one or more SPD bytes from a DIMM.
  *           Start with offset zero and read sequentially.
- *           Optimization relies on autoincrement to avoid 
+ *           Optimization relies on autoincrement to avoid
  *           sending offset for every byte.
  *          Reads 128 bytes in 7-8 ms at 400 KHz.
  */
@@ -127,7 +127,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }
-   
+
    return 0;
    }
 
@@ -150,11 +150,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
    {
    int spdAddress, ioBase;
 
-   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR; 
-   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR; 
+   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
+   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;
    if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
-   
-   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; 
+
+   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
    if (spdAddress == 0) return AGESA_ERROR;
    ioBase = SMBUS_BASE_ADDR;
    setupFch (ioBase);
diff --git a/src/mainboard/amd/inagua/dimmSpd.h b/src/mainboard/amd/inagua/dimmSpd.h
index 069c34a6fc..069c34a6fc 100755..100644
--- a/src/mainboard/amd/inagua/dimmSpd.h
+++ b/src/mainboard/amd/inagua/dimmSpd.h
diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
index fedab7531a..ab58c99aea 100644
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ b/src/mainboard/amd/inagua/get_bus_conf.c
@@ -79,22 +79,22 @@ void get_bus_conf(void)
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are 
- * written into RAM.  The routine that is responsible for writing the tables is 
- * "write_tables", called near the end of "hardwaremain".  There is no platform 
- * specific entry point between the S3 resume decision point and the call to 
- * "write_tables", and the next platform specific entry points are the calls to 
- * the ACPI table write functions.  The first of ose would seem to be the right 
- * place, but other table write functions, e.g. the PIRQ table write function, are 
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM.  The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions.  The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
-  status = agesawrapper_amdinitlate(); 
+  status = agesawrapper_amdinitlate();
   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }
-  
+
   sbdn_sb800 = 0;
 
   for (i = 0; i < 3; i++) {
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index fa7de7d122..7278936902 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -37,15 +37,15 @@ extern u32 sbdn_sb800;
 u32 apicid_sb800;
 
 u8 picr_data[] = {
-  0x0B,0x0A,0x0B,0x05,0x1F,0x1F,0x1F,0x1F,0x50,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 
-  0x1F,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 
+  0x0B,0x0A,0x0B,0x05,0x1F,0x1F,0x1F,0x1F,0x50,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+  0x1F,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0A,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0A,0x0B,0x05
 };
 u8 intr_data[] = {
-  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 
+  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
   0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
       0, apic_version,
       cpu_flag, cpu_features, cpu_feature_flags
     );
-  
+
   cpu_flag = MPC_CPU_ENABLED;
   smp_write_processor(mc,
       1, apic_version,
@@ -112,11 +112,11 @@ static void *smp_write_config_table(void *v)
   my_smp_write_bus(mc, bus_isa, "ISA   ");
 
   /* I/O APICs:   APIC ID Version State   Address */
-  
+
   device_t dev;
   u32 dword;
   u8 byte;
-    
+
   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
   /* Set IO APIC ID onto IO_APIC_ID */
@@ -124,13 +124,13 @@ static void *smp_write_config_table(void *v)
   write32 (dword + 0x10, IO_APIC_ID << 24);
   apicid_sb800 = IO_APIC_ID;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-  
+
   /* PIC IRQ routine */
   for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
     outb(byte, 0xC00);
     outb(picr_data[byte], 0xC01);
   }
-  
+
   /* APIC IRQ routine */
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
     outb(byte | 0x80, 0xC00);
@@ -168,12 +168,12 @@ static void *smp_write_config_table(void *v)
 
   /* SMBUS */
   PCI_INT(0x0, 0x14, 0x0, 0x10);
-  
+
   /* HD Audio */
   PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
-  
+
   /* USB */
-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); 
+  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
   PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
   PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
   PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
@@ -187,7 +187,7 @@ static void *smp_write_config_table(void *v)
 
 
   /* on board NIC & Slot PCIE.  */
-  
+
   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
index 3fb0e875db..3cfd741755 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -91,7 +91,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       return CalloutStatus;
     }
   }
- 
+
   return CalloutStatus;
 }
 
@@ -289,7 +289,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
     } else {
       /* Otherwise, add freed node to the start of the list
-         Update NextNodeOffset and BufferSize to include the 
+         Update NextNodeOffset and BufferSize to include the
          size of BIOS_BUFFER_NODE
       */
       AllocNodePtr->NextNodeOffset = FreedNodeOffset;
@@ -470,7 +470,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-   
+
   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
@@ -563,13 +563,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 &= ~(UINT8)BIT6 ; 
+        Data8 &= ~(UINT8)BIT6 ;
         Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
@@ -586,7 +586,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
         Status = AGESA_SUCCESS;
         break;
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h
index b187fa25c0..b7c78830b4 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.h
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.h
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #ifndef _BIOS_CALLOUT_H_
 #define _BIOS_CALLOUT_H_
 
diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c
index 59d31efb77..b0389b82d9 100644
--- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c
+++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c
@@ -86,7 +86,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-        }       
+        }
 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {
@@ -118,8 +118,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   //
   // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   //
-  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  + 
-                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 + 
+  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
+                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
                                          sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
 
   AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
@@ -127,10 +127,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-    ASSERT(FALSE); 
+    ASSERT(FALSE);
     return;
   }
-  
+
   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
@@ -138,7 +138,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
   BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
- 
+
   LibAmdMemFill (BrazosPcieComplexListPtr,
                    0,
                    sizeof (PCIe_COMPLEX_DESCRIPTOR),
@@ -148,7 +148,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
                    0,
                    sizeof (PCIe_PORT_DESCRIPTOR) * 5,
                    &InitEarly->StdHeader);
-     
+
   LibAmdMemFill (BrazosPcieDdiPtr,
                    0,
                    sizeof (PCIe_DDI_DESCRIPTOR) * 2,
@@ -162,7 +162,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 
-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; 
-  InitEarly->GnbConfig.PsppPolicy      = 0; 
+  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+  InitEarly->GnbConfig.PsppPolicy      = 0;
 }
 
diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
index f35d8db723..b51089f7f6 100644
--- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
@@ -25,42 +25,42 @@
 #include "amdlib.h"
 
 //GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
@@ -68,5 +68,5 @@ VOID
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );
-  
+
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c
index 74aa73d49f..9d9f864141 100644
--- a/src/mainboard/amd/persimmon/agesawrapper.c
+++ b/src/mainboard/amd/persimmon/agesawrapper.c
@@ -86,11 +86,11 @@ agesawrapper_amdinitcpuio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
-  
+
   /* Enable legacy video routing: D18F1xF4 VGA Enable */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
   PciData = 1;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
   /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
    * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
@@ -99,21 +99,21 @@ agesawrapper_amdinitcpuio (
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
   PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
   PciData |= 1 << 7;    // set NP (non-posted) bit
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
   PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
   /* Map the remaining PCI hole as posted MMIO */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
   PciData = 0x00FECF00; // last address before non-posted range
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
   /* Send all IO (0000-FFFF) to southbridge. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
   PciData = 0x0000F000;
@@ -135,7 +135,7 @@ agesawrapper_amdinitmmio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
-  
+
   UINT8                         BusRangeVal = 0;
   UINT8                         BusNum;
   UINT8                         Index;
@@ -166,10 +166,10 @@ agesawrapper_amdinitmmio (
   /* Set Ontario Link Data */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
   PciData = 0x01308002;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
@@ -313,7 +313,7 @@ agesawrapper_amdinitenv (
   /* Initialize Subordinate Bus Number and Secondary Bus Number
    * In platform BIOS this address is allocated by PCI enumeration code
      Modify D1F0x18
-   */  
+   */
   PciAddress.Address.Bus = 0;
   PciAddress.Address.Device = 1;
   PciAddress.Address.Function = 0;
@@ -480,10 +480,10 @@ agesawrapper_amdinitlate (
   return (UINT32)Status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdlaterunaptask (
-  UINT32 Func, 
-  UINT32 Data, 
+  UINT32 Func,
+  UINT32 Data,
   VOID *ConfigPtr
   )
 {
diff --git a/src/mainboard/amd/persimmon/dimmSpd.c b/src/mainboard/amd/persimmon/dimmSpd.c
index 9da0e0e3a8..2bd27d6f42 100644
--- a/src/mainboard/amd/persimmon/dimmSpd.c
+++ b/src/mainboard/amd/persimmon/dimmSpd.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"
@@ -55,7 +55,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
    UINT64 limit;
 
    address |= 1; // set read bit
-   
+
    __outbyte (iobase + 0, 0xFF);                // clear error status
    __outbyte (iobase + 1, 0x1F);                // clear error status
    __outbyte (iobase + 3, offset);              // offset in eeprom
@@ -112,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
  *
  * readspd - Read one or more SPD bytes from a DIMM.
  *           Start with offset zero and read sequentially.
- *           Optimization relies on autoincrement to avoid 
+ *           Optimization relies on autoincrement to avoid
  *           sending offset for every byte.
  *          Reads 128 bytes in 7-8 ms at 400 KHz.
  */
@@ -131,7 +131,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }
-   
+
    return 0;
    }
 
@@ -154,11 +154,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
    {
    int spdAddress, ioBase;
 
-   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR; 
-   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR; 
+   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
+   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;
    if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
-   
-   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; 
+
+   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
    if (spdAddress == 0) return AGESA_ERROR;
    ioBase = 0xB00;
    setupFch (ioBase);
diff --git a/src/mainboard/amd/persimmon/dimmSpd.h b/src/mainboard/amd/persimmon/dimmSpd.h
index 069c34a6fc..069c34a6fc 100755..100644
--- a/src/mainboard/amd/persimmon/dimmSpd.h
+++ b/src/mainboard/amd/persimmon/dimmSpd.h
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
index 4bc5b48218..2d28023574 100644
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ b/src/mainboard/amd/persimmon/get_bus_conf.c
@@ -69,22 +69,22 @@ void get_bus_conf(void)
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are 
- * written into RAM.  The routine that is responsible for writing the tables is 
- * "write_tables", called near the end of "hardwaremain".  There is no platform 
- * specific entry point between the S3 resume decision point and the call to 
- * "write_tables", and the next platform specific entry points are the calls to 
- * the ACPI table write functions.  The first of ose would seem to be the right 
- * place, but other table write functions, e.g. the PIRQ table write function, are 
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM.  The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions.  The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
-  status = agesawrapper_amdinitlate(); 
+  status = agesawrapper_amdinitlate();
   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }
-	
+
   sbdn_sb800 = 0;
 
   for (i = 0; i < 3; i++) {
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index a3b4b5c95e..546d9bd393 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -61,10 +61,10 @@ static void *smp_write_config_table(void *v)
   mptable_write_buses(mc, NULL, &bus_isa);
 
   /* I/O APICs:   APIC ID Version State   Address */
-  
+
   u32 dword;
   u8 byte;
-    
+
   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
@@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v)
   /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
 
   /* on board NIC & Slot PCIE.  */
-  
+
   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
index 126b464305..65ac2e641c 100644
--- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
@@ -57,7 +57,7 @@ void hardwaremain(int ret_addr)
 	train_ram(id.nodeid, sysinfo, sysinfox);
 
 	/*
-	 * go back, but can not use stack any more, because we 
+	 * go back, but can not use stack any more, because we
 	 * only keep ret_addr and can not restore esp, and ebp.
 	 */
 
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index 357bdac230..357bdac230 100755..100644
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 52cab42eb4..52cab42eb4 100755..100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c
index 355077f189..355077f189 100755..100644
--- a/src/mainboard/amd/torpedo/BiosCallOuts.c
+++ b/src/mainboard/amd/torpedo/BiosCallOuts.c
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.h b/src/mainboard/amd/torpedo/BiosCallOuts.h
index 4be7a04c28..4be7a04c28 100755..100644
--- a/src/mainboard/amd/torpedo/BiosCallOuts.h
+++ b/src/mainboard/amd/torpedo/BiosCallOuts.h
diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h
index a7109dc382..a7109dc382 100755..100644
--- a/src/mainboard/amd/torpedo/Oem.h
+++ b/src/mainboard/amd/torpedo/Oem.h
diff --git a/src/mainboard/amd/torpedo/OptionsIds.h b/src/mainboard/amd/torpedo/OptionsIds.h
index e3a1d73add..e3a1d73add 100755..100644
--- a/src/mainboard/amd/torpedo/OptionsIds.h
+++ b/src/mainboard/amd/torpedo/OptionsIds.h
diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c
index 2d011d97a4..2d011d97a4 100755..100644
--- a/src/mainboard/amd/torpedo/PlatformGnbPcie.c
+++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c
diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
index f35d8db723..b51089f7f6 100755..100644
--- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
@@ -25,42 +25,42 @@
 #include "amdlib.h"
 
 //GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
@@ -68,5 +68,5 @@ VOID
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );
-  
+
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c
index 7f4f2d9466..4710b57c2a 100755..100644
--- a/src/mainboard/amd/torpedo/acpi_tables.c
+++ b/src/mainboard/amd/torpedo/acpi_tables.c
@@ -62,13 +62,13 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
-  
+
   /* create all subtables for processors */
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 2);
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 3);
-  
+
   /* Write SB900 IOAPIC, only one */
   current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb900,
              IO_APIC_ADDR, 0);
@@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current)
             current, 0, 0, 2, 0);
   current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
             current, 0, 9, 9, 0xF);
-  
+
   /* 0: mean bus 0--->ISA */
   /* 0: PIC 0 */
   /* 2: APIC 2 */
diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c
index 2995856ec4..2995856ec4 100755..100644
--- a/src/mainboard/amd/torpedo/agesawrapper.c
+++ b/src/mainboard/amd/torpedo/agesawrapper.c
diff --git a/src/mainboard/amd/torpedo/agesawrapper.h b/src/mainboard/amd/torpedo/agesawrapper.h
index c3209f5f49..c3209f5f49 100755..100644
--- a/src/mainboard/amd/torpedo/agesawrapper.h
+++ b/src/mainboard/amd/torpedo/agesawrapper.h
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
index 0379a812e4..0379a812e4 100755..100644
--- a/src/mainboard/amd/torpedo/buildOpts.c
+++ b/src/mainboard/amd/torpedo/buildOpts.c
diff --git a/src/mainboard/amd/torpedo/chip.h b/src/mainboard/amd/torpedo/chip.h
index a252705293..a252705293 100755..100644
--- a/src/mainboard/amd/torpedo/chip.h
+++ b/src/mainboard/amd/torpedo/chip.h
diff --git a/src/mainboard/amd/torpedo/dimmSpd.c b/src/mainboard/amd/torpedo/dimmSpd.c
index 55fb2c3b22..55fb2c3b22 100755..100644
--- a/src/mainboard/amd/torpedo/dimmSpd.c
+++ b/src/mainboard/amd/torpedo/dimmSpd.c
diff --git a/src/mainboard/amd/torpedo/dimmSpd.h b/src/mainboard/amd/torpedo/dimmSpd.h
index 069c34a6fc..069c34a6fc 100755..100644
--- a/src/mainboard/amd/torpedo/dimmSpd.h
+++ b/src/mainboard/amd/torpedo/dimmSpd.h
diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c
index 5701dabc22..5701dabc22 100755..100644
--- a/src/mainboard/amd/torpedo/fadt.c
+++ b/src/mainboard/amd/torpedo/fadt.c
diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c
index f9b4c84eb6..13019ff91f 100755..100644
--- a/src/mainboard/amd/torpedo/get_bus_conf.c
+++ b/src/mainboard/amd/torpedo/get_bus_conf.c
@@ -79,23 +79,23 @@ void get_bus_conf(void)
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are 
- * written into RAM.  The routine that is responsible for writing the tables is 
- * "write_tables", called near the end of "hardwaremain".  There is no platform 
- * specific entry point between the S3 resume decision point and the call to 
- * "write_tables", and the next platform specific entry points are the calls to 
- * the ACPI table write functions.  The first of ose would seem to be the right 
- * place, but other table write functions, e.g. the PIRQ table write function, are 
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM.  The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions.  The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
-  status = agesawrapper_amdinitlate(); 
+  status = agesawrapper_amdinitlate();
   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }
   printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n");
-  
+
   sbdn_sb900 = 0;
 
   for (i = 0; i < 3; i++) {
diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c
index 14dcd2c57b..2633fb5782 100755..100644
--- a/src/mainboard/amd/torpedo/gpio.c
+++ b/src/mainboard/amd/torpedo/gpio.c
@@ -21,7 +21,7 @@
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */
- 
+
 #include "Filecode.h"
 #include "Hudson-2.h"
 #include "AmdSbLib.h"
@@ -63,12 +63,12 @@
  *----------------------------------------------------------------------------------------
  */
 	void gpioEarlyInit (void);
- 
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
- 
+
 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
@@ -98,7 +98,7 @@ gpioEarlyInit(
 	Data8 |= BIT0;
 	WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
 	// Get HUDSON MMIO Base (AcpiMmioAddr)
-	ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);  
+	ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);
 	Data16 = Data8 << 8;
 	ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
 	Data16 |= Data8;
@@ -113,14 +113,14 @@ gpioEarlyInit(
 	Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
 	StripInfo = (Data8 & BIT7) >> 7;
 	Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
-	StripInfo |= (Data8 & BIT7) >> 6;	  
-	if (StripInfo < boardRevC) { 		// for old board. Rev B 
+	StripInfo |= (Data8 & BIT7) >> 6;
+	if (StripInfo < boardRevC) { 		// for old board. Rev B
 		Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3);		// function 3
-		Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0);		// function 0	 
+		Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0);		// function 0
 	}
 	for (Index = 0; Index < MAX_GPIO_NO; Index++) {
 		if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {
-			if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {  
+			if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {
 				// Configure multi-funtion
 				Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
 			}
@@ -138,7 +138,7 @@ gpioEarlyInit(
 		// Configure GEVENT
 		if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
 			SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
-    
+
 			andMask32 = ~(1 << (Index - GEVENT_00));
 
 			//EventEnable: 0-Disable, 1-Enable
@@ -159,12 +159,12 @@ gpioEarlyInit(
 			//SciMap: 00000b ~ 11111b
 			RegIndex8=(u8)((Index - GEVENT_00) >> 2);
 			Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8);
-			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));        
-      
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
+
 			//SmiTrig: 0-Active Low, 1-Active High
 			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
-    
-			//SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 
+
+			//SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13
 			RegIndex8=(u8)((Index - GEVENT_00) >> 4);
 			Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2);
 			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
@@ -180,7 +180,7 @@ gpioEarlyInit(
 	//	GPIO45: Output for MXM Power Enable, active HIGH
 	//	GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
 	//	GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
-	//	
+	//
 		// set INTE#/GPIO32 as GPO for PCIE_SW
 		RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1);      // GPIO
 		RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0);       // GPO
@@ -224,7 +224,7 @@ gpioEarlyInit(
 		//Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20));
 		//Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20)));
 
-		// check if there any GFX card		
+		// check if there any GFX card
 		Flags = 0;
 		// Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL);
 		// Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09);
@@ -244,13 +244,13 @@ gpioEarlyInit(
 			RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
 
 			// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
-			RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);	
-		    
-			//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)	
+			RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);
+
+			//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
 			SbStall (10000);
 
 			// Write the GPIO55(MXM_PWR_EN) to enable the integrated power module
-			RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);	
+			RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);
 
 			//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
 			// WAIT POWER READY: GPIO28 (MXM_PWRGD)
@@ -261,7 +261,7 @@ gpioEarlyInit(
 				ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
 			}
 			// [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset
-		    //	RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);	
+		    //	RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);
 		}
 		else
 		{
@@ -270,9 +270,9 @@ gpioEarlyInit(
 
 			//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
 			SbStall (10000);
-	
+
 			// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down
-			RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); 			  						
+			RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0);
 		}
 
 	//
@@ -288,7 +288,7 @@ gpioEarlyInit(
 		RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6);       // output HIGH
 		RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
 
-		// Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: 
+		// Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN:
 		RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1);          // GPIO
 //		RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0);           // GPO
 		RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6);        // output HIGH
@@ -298,7 +298,7 @@ gpioEarlyInit(
 		// set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ#
 		RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0);          // CLK_REQ3#
 		RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0);       // Enable GPP_CLK3
-		
+
 	//
 	// APU GPP1: WUSB
 	//	GPIO1: MPCIE_RST2#, LOW active
@@ -354,7 +354,7 @@ gpioEarlyInit(
 	//	GPIO41: CLKREQ#
 	//	Clock: GPP_CLK8
 	//
-		// Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: 
+		// Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON:
 		RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2);         // GPIO
 //		RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0);          // GPO
 		RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);       // output HIGH
@@ -382,8 +382,8 @@ gpioEarlyInit(
 		if (!CONFIG_ONBOARD_LAN)
 		{ // 1 - DISABLED
 			RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0);      // LOM_POWER off
-			RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);	
-			RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3);    // PULL UP - DISABLED	
+			RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);
+			RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3);    // PULL UP - DISABLED
 			RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0);     // Disable GPP_CLK3
 		}
 //		else
@@ -409,11 +409,11 @@ gpioEarlyInit(
 //		else
 //		{ // 0 - AUTO
 //			// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH)
-//			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); 
+//			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
 //			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
 //
 //			RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);
-//			RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);	
+//			RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);
 //		}
 
 //
@@ -430,7 +430,7 @@ gpioEarlyInit(
 		RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
 		RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
 		RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3);   // PULL_UP DISABLE
-		RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0);    // DISABLE GPP_CLK7 	
+		RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0);    // DISABLE GPP_CLK7
 		RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0);  // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
 		}
 //	}
@@ -447,25 +447,25 @@ if (!CONFIG_ONBOARD_BLUETOOTH) {
 }
 
 //
-// WebCam control: 
+// WebCam control:
 //    amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
 //       GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
 //
 if (!CONFIG_ONBOARD_WEBCAM) {
 //-	if (SystemConfiguration.amdWebCam == 1) {
 		RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
-//-	}  
+//-	}
 }
 
 //
-// Travis enable: 
+// Travis enable:
 //    amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
 //           GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
 //
 if (!CONFIG_ONBOARD_TRAVIS) {
 //-	if (SystemConfiguration.amdTravisCtrl == 0) {
 		RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
-//-	} 
+//-	}
 }
 
 //
diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h
index 159394e292..45394efe1d 100755..100644
--- a/src/mainboard/amd/torpedo/gpio.h
+++ b/src/mainboard/amd/torpedo/gpio.h
@@ -21,8 +21,8 @@
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */
- 
-  
+
+
 #ifndef _GPIO_H_
 #define _GPIO_H_
 
@@ -121,8 +121,8 @@
 #define GPIO_18_SELECT      FUNCTION0+NonGpio   // NOT USED
 #define GPIO_19_SELECT      FUNCTION1           // For LASSO_DET# detection when Gevent14# is asserted.
 #define GPIO_20_SELECT      FUNCTION1           // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option)
-#define GPIO_21_SELECT      FUNCTION1           // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) 
-#define GPIO_22_SELECT      FUNCTION1           // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE 
+#define GPIO_21_SELECT      FUNCTION1           // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option)
+#define GPIO_22_SELECT      FUNCTION1           // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE
                                                 //      1:BATTERY IS FINE(DEFAULT)
                                                 //      0:BATTERY IS LOW
 #define GPIO_23_SELECT      FUNCTION1	        // CODEC_ON.1: CODEC ON (default)0: CODEC OFF
@@ -143,7 +143,7 @@
                                                 //      0:USB3.0 I/F in Express CARD
                                                 //      1:PCIE I/F  in Express CARD detection
 #define GPIO_34_SELECT      FUNCTION1           // WEBCAM_ON#. 0: ON (default) 1: OFF
-#define GPIO_35_SELECT      FUNCTION1           // ODD_DA_INTH# 
+#define GPIO_35_SELECT      FUNCTION1           // ODD_DA_INTH#
 #define GPIO_36_SELECT      FUNCTION0+NonGpio   // PCICLK FOR KBC
 #define GPIO_37_SELECT      FUNCTION0+NonGpio   // NOT USED
 #define GPIO_38_SELECT      FUNCTION0+NonGpio   // NOT USED
@@ -152,7 +152,7 @@
 #define GPIO_41_SELECT      FUNCTION1+NonGpio   // 1394 CLK REQ#
 #define GPIO_42_SELECT      FUNCTION1+NonGpio   // X4 GPP CLK REQ#
 #define GPIO_43_SELECT      FUNCTION0+NonGpio   // SMBUS0, CLOCK
-#define GPIO_44_SELECT      FUNCTION1+NonGpio   // PEGPIO0, RESET THE MXM MODULE 
+#define GPIO_44_SELECT      FUNCTION1+NonGpio   // PEGPIO0, RESET THE MXM MODULE
 #define GPIO_45_SELECT      FUNCTION2+NonGpio   // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF
 #define GPIO_46_SELECT      FUNCTION1+NonGpio   // USB3.0_CLKREQ#
 #define GPIO_47_SELECT      FUNCTION0+NonGpio   // SMBUS0, DATA
@@ -215,7 +215,7 @@
 #define GPIO_101_SELECT     FUNCTION1           // LPC_PD#/GEVENT5# -> hotplug of express card, low active
 #define GPIO_102_SELECT     FUNCTION0+NonGpio   // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED,
                                                 // there is a confliction to IR function when this pin is as a GEVENT.
-#define GPIO_103_SELECT     FUNCTION0+NonGpio   // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, 
+#define GPIO_103_SELECT     FUNCTION0+NonGpio   // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD,
                                                 // special pin difination for SB900 VGA OUTPUT, high active,
                                                 // VGA power for Hudson-M2 will be down when it was asserted.
 #define GPIO_104_SELECT     FUNCTION0           // WAKE#/GEVENT8# -> WAKEUP, low active
@@ -223,7 +223,7 @@
 #define GPIO_106_SELECT     FUNCTION0           // GBE_LED2/GEVENT10# -> GBE_LED2
 #define GPIO_107_SELECT     FUNCTION0+NonGpio   // GBE_STAT0/GEVENT11# -> GBE_STAT0
 #define GPIO_108_SELECT     FUNCTION2           // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active
-                                                // [option for SPI_TPM_CS# in Hudson-M2 A12)] 
+                                                // [option for SPI_TPM_CS# in Hudson-M2 A12)]
 #define GPIO_109_SELECT     FUNCTION0           // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) &
                                                 //  USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time
 #define GPIO_110_SELECT     FUNCTION2           // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect,
@@ -238,7 +238,7 @@
 #define GPIO_115_SELECT     FUNCTION0           // SYS_RESET#/GEVENT19# -> SYS_RST#
 #define GPIO_116_SELECT     FUNCTION0           // R_RX1/GEVENT20# -> IR INPUT
 #define GPIO_117_SELECT     FUNCTION1+NonGpio   // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1
-#define GPIO_118_SELECT     FUNCTION1           // RI#/GEVENT22# -> LID_CLOSED# 
+#define GPIO_118_SELECT     FUNCTION1           // RI#/GEVENT22# -> LID_CLOSED#
 #define GPIO_119_SELECT     FUNCTION0           // LPC_SMI#/GEVENT23# -> EC_SMI
 #define GPIO_120_SELECT     FUNCTION0+NonGpio
 #define GPIO_121_SELECT     FUNCTION0+NonGpio
@@ -287,7 +287,7 @@
 #define GPIO_162_SELECT     FUNCTION0+NonGpio   // SPI ROM
 #define GPIO_163_SELECT     FUNCTION0+NonGpio   // SPI ROM
 #define GPIO_164_SELECT     FUNCTION0+NonGpio   // SPI ROM
-#define GPIO_165_SELECT     FUNCTION0+NonGpio   // SPI ROM 
+#define GPIO_165_SELECT     FUNCTION0+NonGpio   // SPI ROM
 #define GPIO_166_SELECT     FUNCTION1+NonGpio   // GBE_STAT2
 #define GPIO_167_SELECT     FUNCTION0+NonGpio   // AZ_SDATA_IN0
 #define GPIO_168_SELECT     FUNCTION0+NonGpio   // AZ_SDATA_IN1
@@ -357,18 +357,18 @@
 
 #define TYPE_GPI  (1<<5)
 #define TYPE_GPO  (0<<5)
-                    
-#define GPIO_00_TYPE        TYPE_GPO 
+
+#define GPIO_00_TYPE        TYPE_GPO
 #define GPIO_01_TYPE        TYPE_GPO
 #define GPIO_02_TYPE        TYPE_GPO
 #define GPIO_03_TYPE        TYPE_GPO
 #define GPIO_04_TYPE        TYPE_GPO
-#define GPIO_05_TYPE        TYPE_GPO 
+#define GPIO_05_TYPE        TYPE_GPO
 #define GPIO_06_TYPE        TYPE_GPO
 #define GPIO_07_TYPE        TYPE_GPO
 #define GPIO_08_TYPE        TYPE_GPO
 #define GPIO_09_TYPE        TYPE_GPI
-#define GPIO_10_TYPE        TYPE_GPI 
+#define GPIO_10_TYPE        TYPE_GPI
 #define GPIO_11_TYPE        TYPE_GPO
 #define GPIO_12_TYPE        TYPE_GPO
 #define GPIO_13_TYPE        TYPE_GPO
@@ -397,33 +397,33 @@
 #define GPIO_36_TYPE        TYPE_GPO
 #define GPIO_37_TYPE        TYPE_GPO
 #define GPIO_38_TYPE        TYPE_GPO
-#define GPIO_39_TYPE        TYPE_GPO 
+#define GPIO_39_TYPE        TYPE_GPO
 #define GPIO_40_TYPE        TYPE_GPO
-#define GPIO_41_TYPE        TYPE_GPI 
+#define GPIO_41_TYPE        TYPE_GPI
 #define GPIO_42_TYPE        TYPE_GPI
 #define GPIO_43_TYPE        TYPE_GPO
 #define GPIO_44_TYPE        TYPE_GPO
 #define GPIO_45_TYPE        TYPE_GPO
 #define GPIO_46_TYPE        TYPE_GPI
 #define GPIO_47_TYPE        TYPE_GPO
-#define GPIO_48_TYPE        TYPE_GPO 
-#define GPIO_49_TYPE        TYPE_GPO 
+#define GPIO_48_TYPE        TYPE_GPO
+#define GPIO_49_TYPE        TYPE_GPO
 #define GPIO_50_TYPE        TYPE_GPO
 #define GPIO_51_TYPE        TYPE_GPO
 #define GPIO_52_TYPE        TYPE_GPO
-#define GPIO_53_TYPE        TYPE_GPO 
-#define GPIO_54_TYPE        TYPE_GPO 
-#define GPIO_55_TYPE        TYPE_GPO 
+#define GPIO_53_TYPE        TYPE_GPO
+#define GPIO_54_TYPE        TYPE_GPO
+#define GPIO_55_TYPE        TYPE_GPO
 #define GPIO_56_TYPE        TYPE_GPI
 #define GPIO_57_TYPE        TYPE_GPO
-#define GPIO_58_TYPE        TYPE_GPO 
+#define GPIO_58_TYPE        TYPE_GPO
 #define GPIO_59_TYPE        TYPE_GPO
 #define GPIO_60_TYPE        TYPE_GPI
 #define GPIO_61_TYPE        TYPE_GPI
 #define GPIO_62_TYPE        TYPE_GPI
 #define GPIO_63_TYPE        TYPE_GPI
 #define GPIO_64_TYPE        TYPE_GPI
-#define GPIO_65_TYPE        TYPE_GPI  
+#define GPIO_65_TYPE        TYPE_GPI
 #define GPIO_66_TYPE        TYPE_GPO
 #define GPIO_67_TYPE        TYPE_GPO
 #define GPIO_68_TYPE        TYPE_GPO
@@ -460,17 +460,17 @@
 #define GPIO_97_TYPE        TYPE_GPI
 #define GPIO_98_TYPE        TYPE_GPI
 #define GPIO_99_TYPE        TYPE_GPI
-#define GPIO_100_TYPE       TYPE_GPI 
+#define GPIO_100_TYPE       TYPE_GPI
 #define GPIO_101_TYPE       TYPE_GPI
 #define GPIO_102_TYPE       TYPE_GPO
 #define GPIO_103_TYPE       TYPE_GPO
 #define GPIO_104_TYPE       TYPE_GPI
-#define GPIO_105_TYPE       TYPE_GPI 
+#define GPIO_105_TYPE       TYPE_GPI
 #define GPIO_106_TYPE       TYPE_GPO
 #define GPIO_107_TYPE       TYPE_GPI
 #define GPIO_108_TYPE       TYPE_GPI
 #define GPIO_109_TYPE       TYPE_GPI
-#define GPIO_110_TYPE       TYPE_GPI 
+#define GPIO_110_TYPE       TYPE_GPI
 #define GPIO_111_TYPE       TYPE_GPI
 #define GPIO_112_TYPE       TYPE_GPI
 #define GPIO_113_TYPE       TYPE_GPI
@@ -500,33 +500,33 @@
 #define GPIO_136_TYPE       TYPE_GPO
 #define GPIO_137_TYPE       TYPE_GPO
 #define GPIO_138_TYPE       TYPE_GPO
-#define GPIO_139_TYPE       TYPE_GPO 
+#define GPIO_139_TYPE       TYPE_GPO
 #define GPIO_140_TYPE       TYPE_GPO
-#define GPIO_141_TYPE       TYPE_GPO 
+#define GPIO_141_TYPE       TYPE_GPO
 #define GPIO_142_TYPE       TYPE_GPO
 #define GPIO_143_TYPE       TYPE_GPO
 #define GPIO_144_TYPE       TYPE_GPO
 #define GPIO_145_TYPE       TYPE_GPO
 #define GPIO_146_TYPE       TYPE_GPO
 #define GPIO_147_TYPE       TYPE_GPO
-#define GPIO_148_TYPE       TYPE_GPO 
-#define GPIO_149_TYPE       TYPE_GPO 
+#define GPIO_148_TYPE       TYPE_GPO
+#define GPIO_149_TYPE       TYPE_GPO
 #define GPIO_150_TYPE       TYPE_GPO
 #define GPIO_151_TYPE       TYPE_GPO
 #define GPIO_152_TYPE       TYPE_GPO
-#define GPIO_153_TYPE       TYPE_GPO 
-#define GPIO_154_TYPE       TYPE_GPO 
-#define GPIO_155_TYPE       TYPE_GPO 
+#define GPIO_153_TYPE       TYPE_GPO
+#define GPIO_154_TYPE       TYPE_GPO
+#define GPIO_155_TYPE       TYPE_GPO
 #define GPIO_156_TYPE       TYPE_GPO
 #define GPIO_157_TYPE       TYPE_GPO
-#define GPIO_158_TYPE       TYPE_GPO 
+#define GPIO_158_TYPE       TYPE_GPO
 #define GPIO_159_TYPE       TYPE_GPO
 #define GPIO_160_TYPE       TYPE_GPO
 #define GPIO_161_TYPE       TYPE_GPO
 #define GPIO_162_TYPE       TYPE_GPO
 #define GPIO_163_TYPE       TYPE_GPO
 #define GPIO_164_TYPE       TYPE_GPI
-#define GPIO_165_TYPE       TYPE_GPO  
+#define GPIO_165_TYPE       TYPE_GPO
 #define GPIO_166_TYPE       TYPE_GPI
 #define GPIO_167_TYPE       TYPE_GPI
 #define GPIO_168_TYPE       TYPE_GPI
@@ -561,17 +561,17 @@
 #define GPIO_197_TYPE       TYPE_GPO
 #define GPIO_198_TYPE       TYPE_GPO
 #define GPIO_199_TYPE       TYPE_GPI
-#define GPIO_200_TYPE       TYPE_GPO 
+#define GPIO_200_TYPE       TYPE_GPO
 #define GPIO_201_TYPE       TYPE_GPI
 #define GPIO_202_TYPE       TYPE_GPI
 #define GPIO_203_TYPE       TYPE_GPI
 #define GPIO_204_TYPE       TYPE_GPI
-#define GPIO_205_TYPE       TYPE_GPI 
+#define GPIO_205_TYPE       TYPE_GPI
 #define GPIO_206_TYPE       TYPE_GPI
 #define GPIO_207_TYPE       TYPE_GPI
 #define GPIO_208_TYPE       TYPE_GPI
 #define GPIO_209_TYPE       TYPE_GPO
-#define GPIO_210_TYPE       TYPE_GPO 
+#define GPIO_210_TYPE       TYPE_GPO
 #define GPIO_211_TYPE       TYPE_GPO
 #define GPIO_212_TYPE       TYPE_GPO
 #define GPIO_213_TYPE       TYPE_GPO
@@ -595,17 +595,17 @@
 #define GPO_LOW   (0<<6)
 #define GPO_HI    (1<<6)
 
-#define GPO_00_LEVEL        GPO_HI 
+#define GPO_00_LEVEL        GPO_HI
 #define GPO_01_LEVEL        GPO_HI
 #define GPO_02_LEVEL        GPO_HI
 #define GPO_03_LEVEL        GPO_HI
 #define GPO_04_LEVEL        GPO_HI
-#define GPO_05_LEVEL        GPO_HI  
+#define GPO_05_LEVEL        GPO_HI
 #define GPO_06_LEVEL        GPO_HI
 #define GPO_07_LEVEL        GPO_HI
 #define GPO_08_LEVEL        GPO_HI
 #define GPO_09_LEVEL        GPO_LOW
-#define GPO_10_LEVEL        GPO_LOW 
+#define GPO_10_LEVEL        GPO_LOW
 #define GPO_11_LEVEL        GPO_HI
 #define GPO_12_LEVEL        GPO_HI
 #define GPO_13_LEVEL        GPO_HI
@@ -634,16 +634,16 @@
 #define GPO_36_LEVEL        GPO_LOW
 #define GPO_37_LEVEL        GPO_HI
 #define GPO_38_LEVEL        GPO_HI
-#define GPO_39_LEVEL        GPO_HI  
+#define GPO_39_LEVEL        GPO_HI
 #define GPO_40_LEVEL        GPO_LOW
-#define GPO_41_LEVEL        GPO_LOW 
+#define GPO_41_LEVEL        GPO_LOW
 #define GPO_42_LEVEL        GPO_LOW
 #define GPO_43_LEVEL        GPO_LOW
 #define GPO_44_LEVEL        GPO_HI
 #define GPO_45_LEVEL        GPO_HI
 #define GPO_46_LEVEL        GPO_LOW
 #define GPO_47_LEVEL        GPO_LOW
-#define GPO_48_LEVEL        GPO_LOW 
+#define GPO_48_LEVEL        GPO_LOW
 #define GPO_49_LEVEL        GPO_HI
 #define GPO_50_LEVEL        GPO_HI
 #define GPO_51_LEVEL        GPO_LOW
@@ -667,7 +667,7 @@
 #define GPO_69_LEVEL        GPO_LOW
 #define GPO_70_LEVEL        GPO_LOW
 #define GPO_71_LEVEL        GPO_LOW
-#define GPO_72_LEVEL        GPO_LOW 
+#define GPO_72_LEVEL        GPO_LOW
 #define GPO_73_LEVEL        GPO_LOW
 #define GPO_74_LEVEL        GPO_LOW
 #define GPO_75_LEVEL        GPO_LOW
@@ -695,17 +695,17 @@
 #define GPO_97_LEVEL        GPO_LOW
 #define GPO_98_LEVEL        GPO_LOW
 #define GPO_99_LEVEL        GPO_LOW
-#define GPO_100_LEVEL       GPO_LOW 
+#define GPO_100_LEVEL       GPO_LOW
 #define GPO_101_LEVEL       GPO_LOW
 #define GPO_102_LEVEL       GPO_LOW
 #define GPO_103_LEVEL       GPO_LOW
 #define GPO_104_LEVEL       GPO_LOW
-#define GPO_105_LEVEL       GPO_LOW  
+#define GPO_105_LEVEL       GPO_LOW
 #define GPO_106_LEVEL       GPO_LOW
 #define GPO_107_LEVEL       GPO_LOW
 #define GPO_108_LEVEL       GPO_HI
 #define GPO_109_LEVEL       GPO_LOW
-#define GPO_110_LEVEL       GPO_HI 
+#define GPO_110_LEVEL       GPO_HI
 #define GPO_111_LEVEL       GPO_HI
 #define GPO_112_LEVEL       GPO_HI
 #define GPO_113_LEVEL       GPO_LOW
@@ -734,16 +734,16 @@
 #define GPO_136_LEVEL       GPO_LOW
 #define GPO_137_LEVEL       GPO_LOW
 #define GPO_138_LEVEL       GPO_LOW
-#define GPO_139_LEVEL       GPO_LOW  
+#define GPO_139_LEVEL       GPO_LOW
 #define GPO_140_LEVEL       GPO_LOW
-#define GPO_141_LEVEL       GPO_LOW 
+#define GPO_141_LEVEL       GPO_LOW
 #define GPO_142_LEVEL       GPO_LOW
 #define GPO_143_LEVEL       GPO_LOW
 #define GPO_144_LEVEL       GPO_LOW
 #define GPO_145_LEVEL       GPO_LOW
 #define GPO_146_LEVEL       GPO_LOW
 #define GPO_147_LEVEL       GPO_LOW
-#define GPO_148_LEVEL       GPO_LOW 
+#define GPO_148_LEVEL       GPO_LOW
 #define GPO_149_LEVEL       GPO_LOW
 #define GPO_150_LEVEL       GPO_LOW
 #define GPO_151_LEVEL       GPO_LOW
@@ -795,17 +795,17 @@
 #define GPO_197_LEVEL       GPO_LOW
 #define GPO_198_LEVEL       GPO_LOW
 #define GPO_199_LEVEL       GPO_LOW
-#define GPO_200_LEVEL       GPO_HI 
+#define GPO_200_LEVEL       GPO_HI
 #define GPO_201_LEVEL       GPO_LOW
 #define GPO_202_LEVEL       GPO_LOW
 #define GPO_203_LEVEL       GPO_LOW
 #define GPO_204_LEVEL       GPO_LOW
-#define GPO_205_LEVEL       GPO_LOW  
+#define GPO_205_LEVEL       GPO_LOW
 #define GPO_206_LEVEL       GPO_LOW
 #define GPO_207_LEVEL       GPO_LOW
 #define GPO_208_LEVEL       GPO_LOW
 #define GPO_209_LEVEL       GPO_LOW
-#define GPO_210_LEVEL       GPO_LOW 
+#define GPO_210_LEVEL       GPO_LOW
 #define GPO_211_LEVEL       GPO_LOW
 #define GPO_212_LEVEL       GPO_LOW
 #define GPO_213_LEVEL       GPO_LOW
@@ -2278,9 +2278,9 @@ typedef struct _GEVENT_SETTINGS
     u8 SciLevl;          // 0: Edge trigger, 1: Level Trigger
     u8 SmiSciEn;         // 0: Not send SMI, 1: Send SMI
     u8 SciS0En;          // 0: Disable, 1: Enable
-    u8 SciMap;           // 0000b->1111b 
+    u8 SciMap;           // 0000b->1111b
     u8 SmiTrig;          // 0: Active Low, 1: Active High
-    u8 SmiControl;       // 0: Disable, 1: SMI 2: NMI 3: IRQ13     
+    u8 SmiControl;       // 0: Disable, 1: SMI 2: NMI 3: IRQ13
 } GEVENT_SETTINGS;
 
 GEVENT_SETTINGS gevent_table[] =
@@ -2315,15 +2315,15 @@ GEVENT_SETTINGS gevent_table[] =
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */
- 
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
- 
+
 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
- 
+
 #endif
diff --git a/src/mainboard/amd/torpedo/irq_tables.c b/src/mainboard/amd/torpedo/irq_tables.c
index f61f1e896b..f61f1e896b 100755..100644
--- a/src/mainboard/amd/torpedo/irq_tables.c
+++ b/src/mainboard/amd/torpedo/irq_tables.c
diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c
index 288798fdb2..288798fdb2 100755..100644
--- a/src/mainboard/amd/torpedo/mainboard.c
+++ b/src/mainboard/amd/torpedo/mainboard.c
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 03812060c8..2e171a1372 100755..100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -37,15 +37,15 @@ extern u32 sbdn_sb900;
 u32 apicid_sb900;
 
 u8 picr_data[] = {
-  0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 
-  0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 
+  0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+  0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0B,0x0B,0x0B
 };
 u8 intr_data[] = {
-  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 
+  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
   0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
       0, apic_version,
       cpu_flag, cpu_features, cpu_feature_flags
     );
-  
+
   cpu_flag = MPC_CPU_ENABLED;
   smp_write_processor(mc,
       1, apic_version,
@@ -112,11 +112,11 @@ static void *smp_write_config_table(void *v)
   my_smp_write_bus(mc, bus_isa, "ISA   ");
 
   /* I/O APICs:   APIC ID Version State   Address */
-  
+
   device_t dev;
   u32 dword;
   u8 byte;
-    
+
   dword = 0;
   dword = pm_ioread(0x34) & 0xF0;
   dword |= (pm_ioread(0x35) & 0xFF) << 8;
@@ -127,13 +127,13 @@ static void *smp_write_config_table(void *v)
   write32 (dword + 0x10, IO_APIC_ID << 24);
   apicid_sb900 = IO_APIC_ID;
   smp_write_ioapic(mc, apicid_sb900, 0x21, dword);
-  
+
   /* PIC IRQ routine */
   for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
     outb(byte, 0xC00);
     outb(picr_data[byte], 0xC01);
   }
-  
+
   /* APIC IRQ routine */
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
     outb(byte | 0x80, 0xC00);
@@ -172,15 +172,15 @@ static void *smp_write_config_table(void *v)
   /* Internal VGA */
   PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
   PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
-  
+
   /* SMBUS */
   PCI_INT(0x0, 0x14, 0x0, 0x10);
-  
+
   /* HD Audio */
   PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
-  
+
   /* USB */
-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); 
+  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
   PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
   PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
   PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
@@ -194,7 +194,7 @@ static void *smp_write_config_table(void *v)
 
 
   /* on board NIC & Slot PCIE.  */
-  
+
   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14);
diff --git a/src/mainboard/amd/torpedo/pmio.c b/src/mainboard/amd/torpedo/pmio.c
index baded54ba6..baded54ba6 100755..100644
--- a/src/mainboard/amd/torpedo/pmio.c
+++ b/src/mainboard/amd/torpedo/pmio.c
diff --git a/src/mainboard/amd/torpedo/pmio.h b/src/mainboard/amd/torpedo/pmio.h
index 207fdc24ab..207fdc24ab 100755..100644
--- a/src/mainboard/amd/torpedo/pmio.h
+++ b/src/mainboard/amd/torpedo/pmio.h
diff --git a/src/mainboard/amd/torpedo/reset.c b/src/mainboard/amd/torpedo/reset.c
index 36bc6e0f17..36bc6e0f17 100755..100644
--- a/src/mainboard/amd/torpedo/reset.c
+++ b/src/mainboard/amd/torpedo/reset.c
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 317f697fea..317f697fea 100755..100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c
index ae67c3fd6e..a0d64a7247 100644
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.c
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #include "agesawrapper.h"
 #include "amdlib.h"
 #include "BiosCallOuts.h"
@@ -61,7 +61,7 @@ CONST BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
   {AGESA_HOOKBEFORE_DQS_TRAINING,
    BiosHookBeforeDQSTraining
   },
-  
+
   {AGESA_HOOKBEFORE_DRAM_INIT,
    BiosHookBeforeDramInit
   },
@@ -149,7 +149,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
        to the end of the allocated nodes list.
       */
-       
+
     }
     /* Find the node that best fits the requested buffer size */
     FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
@@ -199,7 +199,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
       /* If BestFitNode is the first buffer in the list, then update
          StartOfFreedNodes to reflect the new free node
-      */         
+      */
       if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
         BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
       } else {
@@ -284,10 +284,10 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       FreedNodePtr->NextNodeOffset = 0;
 
     } else {
-      /* Otherwise, add freed node to the start of the list 
-         Update NextNodeOffset and BufferSize to include the 
+      /* Otherwise, add freed node to the start of the list
+         Update NextNodeOffset and BufferSize to include the
          size of BIOS_BUFFER_NODE
-      */   
+      */
       AllocNodePtr->NextNodeOffset = FreedNodeOffset;
     }
     /* Update StartOfFreedNodes to the new first node */
@@ -295,7 +295,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   } else {
     /* Traverse list of freed nodes to find where the deallocated node
        should be place
-    */   
+    */
     NextNodeOffset = FreedNodeOffset;
     NextNodePtr = FreedNodePtr;
     while (AllocNodeOffset > NextNodeOffset) {
@@ -309,7 +309,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
     /* If deallocated node is adjacent to the next node,
        concatenate both nodes
-    */   
+    */
     if (NextNodeOffset == EndNodeOffset) {
       NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
       AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
@@ -323,7 +323,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
     }
     /* If deallocated node is adjacent to the previous node,
        concatenate both nodes
-    */   
+    */
     PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
     EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
     if (AllocNodeOffset == EndNodeOffset) {
@@ -387,10 +387,10 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   UINT8                 Value;
   UINTN               ResetType;
   AMD_CONFIG_PARAMS   *StdHeader;
-  
+
   ResetType = Data;
   StdHeader = ConfigPtr;
-    
+
   //
   // Perform the RESET based upon the ResetType. In case of
   // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
@@ -402,17 +402,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   case WARM_RESET_WHENEVER:
   case COLD_RESET_WHENEVER:
     break;
-    
+
   case WARM_RESET_IMMEDIATELY:
   case COLD_RESET_IMMEDIATELY:
       Value = 0x06;
       LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
     break;
-    
+
   default:
     break;
   }
-  
+
   Status = 0;
   return Status;
 }
@@ -445,10 +445,10 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   UINT8             Data8;
   UINT16            Data16;
   UINT8             TempData8;
-    
+
   FcnData = Data;
   MemData = ConfigPtr;
-  
+
   Status  = AGESA_SUCCESS;
   /* Get SB800 MMIO Base (AcpiMmioAddr) */
   WriteIo8 (0xCD6, 0x27);
@@ -459,14 +459,14 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   Data16  |= Data8;
   AcpiMmioAddr = (UINT32)Data16 << 16;
   GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-  
+
   Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
   Data8 &= ~BIT5;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-   
+
   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
@@ -485,7 +485,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   TempData8 &= 0x23;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-  
+
   switch(MemData->ParameterListPtr->DDR3Voltage){
     case VOLT1_35:
       Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
@@ -527,12 +527,12 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   AGESA_STATUS Status;
   UINTN                 FcnData;
   PCIe_SLOT_RESET_INFO  *ResetInfo;
-  
+
   UINT32  GpioMmioAddr;
   UINT32  AcpiMmioAddr;
   UINT8   Data8;
   UINT16  Data16;
-  
+
   FcnData   = Data;
   ResetInfo = ConfigPtr;
   // Get SB800 MMIO Base (AcpiMmioAddr)
@@ -552,13 +552,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 &= ~(UINT8)BIT6 ; 
+        Data8 &= ~(UINT8)BIT6 ;
         Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
@@ -575,7 +575,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
         Status = AGESA_SUCCESS;
         break;
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.h b/src/mainboard/asrock/e350m1/BiosCallOuts.h
index 2912ec6f51..4efe15fa4d 100644
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.h
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.h
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #ifndef _BIOS_CALLOUT_H_
 #define _BIOS_CALLOUT_H_
 
@@ -45,7 +45,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 
 /* REQUIRED CALLOUTS
  * AGESA ADVANCED CALLOUTS - CPU
- */  
+ */
 AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c
index 0d790773d4..a79dfab62e 100644
--- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c
+++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c
@@ -86,7 +86,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-        }       
+        }
 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {
@@ -118,8 +118,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   //
   // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   //
-  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  + 
-                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 + 
+  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
+                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
                                          sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
 
   AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
@@ -127,10 +127,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-    ASSERT(FALSE); 
+    ASSERT(FALSE);
     return Status;
   }
-  
+
   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
@@ -138,7 +138,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
   BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
- 
+
   LibAmdMemFill (BrazosPcieComplexListPtr,
                    0,
                    sizeof (PCIe_COMPLEX_DESCRIPTOR),
@@ -148,7 +148,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
                    0,
                    sizeof (PCIe_PORT_DESCRIPTOR) * 5,
                    &InitEarly->StdHeader);
-     
+
   LibAmdMemFill (BrazosPcieDdiPtr,
                    0,
                    sizeof (PCIe_DDI_DESCRIPTOR) * 2,
@@ -162,7 +162,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 
-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; 
-  InitEarly->GnbConfig.PsppPolicy      = 0; 
+  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+  InitEarly->GnbConfig.PsppPolicy      = 0;
 }
 
diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h
index f35d8db723..b51089f7f6 100644
--- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h
+++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h
@@ -25,42 +25,42 @@
 #include "amdlib.h"
 
 //GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
@@ -68,5 +68,5 @@ VOID
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );
-  
+
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c
index 802e00e1fe..7fc2fd6da4 100644
--- a/src/mainboard/asrock/e350m1/agesawrapper.c
+++ b/src/mainboard/asrock/e350m1/agesawrapper.c
@@ -21,7 +21,7 @@
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */
- 
+
 #include <stdint.h>
 #include <string.h>
 #include "agesawrapper.h"
@@ -52,8 +52,8 @@ VOID *AcpiSlit    = NULL;
 
 VOID *AcpiWheaMce = NULL;
 VOID *AcpiWheaCmc = NULL;
-VOID *AcpiAlib    = NULL; 
- 
+VOID *AcpiAlib    = NULL;
+
 
 /*----------------------------------------------------------------------------------------
  *                  T Y P E D E F S     A N D     S T R U C T U  R E S
@@ -64,17 +64,17 @@ VOID *AcpiAlib    = NULL;
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */
- 
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
- 
+
 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
-UINT32 
+UINT32
 agesawrapper_amdinitcpuio (
   VOID
   )
@@ -84,11 +84,11 @@ agesawrapper_amdinitcpuio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
-  
+
   /* Enable legacy video routing: D18F1xF4 VGA Enable */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
   PciData = 1;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
   /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
    * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
@@ -97,21 +97,21 @@ agesawrapper_amdinitcpuio (
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
   PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
   PciData |= 1 << 7;    // set NP (non-posted) bit
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
   PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
   /* Map the remaining PCI hole as posted MMIO */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
   PciData = 0x00FECF00; // last address before non-posted range
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
   /* Send all IO (0000-FFFF) to southbridge. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
   PciData = 0x0000F000;
@@ -122,8 +122,8 @@ agesawrapper_amdinitcpuio (
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 }
- 
-UINT32 
+
+UINT32
 agesawrapper_amdinitmmio (
   VOID
   )
@@ -133,7 +133,7 @@ agesawrapper_amdinitmmio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
-  
+
   /*
    Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
    Address MSR register.
@@ -141,27 +141,27 @@ agesawrapper_amdinitmmio (
 
   MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
   LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
-  
+
   /*
    Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
   */
   LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
   MsrReg = MsrReg | 0x0000400000000000;
   LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-  
+
   /* Set Ontario Link Data */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
   PciData = 0x01308002;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdinitreset (
   VOID
   )
@@ -169,7 +169,7 @@ agesawrapper_amdinitreset (
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
   AMD_RESET_PARAMS AmdResetParams;
-  
+
   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),
@@ -191,14 +191,14 @@ agesawrapper_amdinitreset (
   AmdParamStruct.StdHeader.ImageBasePtr = 0;
   AmdCreateStruct (&AmdParamStruct);
   AmdResetParams.HtConfig.Depth = 0;
-  
+
   status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
   if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
   AmdReleaseStruct (&AmdParamStruct);
   return (UINT32)status;
- }  
-  
-UINT32 
+ }
+
+UINT32
 agesawrapper_amdinitearly (
   VOID
   )
@@ -206,7 +206,7 @@ agesawrapper_amdinitearly (
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
   AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
-  
+
   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),
@@ -219,10 +219,10 @@ agesawrapper_amdinitearly (
   AmdParamStruct.StdHeader.Func = 0;
   AmdParamStruct.StdHeader.ImageBasePtr = 0;
   AmdCreateStruct (&AmdParamStruct);
-  
+
   AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
   OemCustomizeInitEarly (AmdEarlyParamsPtr);
-  
+
   status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
   if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
   AmdReleaseStruct (&AmdParamStruct);
@@ -230,7 +230,7 @@ agesawrapper_amdinitearly (
   return (UINT32)status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdinitpost (
   VOID
   )
@@ -272,7 +272,7 @@ agesawrapper_amdinitpost (
   return (UINT32)status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdinitenv (
   VOID
   )
@@ -299,7 +299,7 @@ agesawrapper_amdinitenv (
   /* Initialize Subordinate Bus Number and Secondary Bus Number
    * In platform BIOS this address is allocated by PCI enumeration code
      Modify D1F0x18
-   */  
+   */
   PciAddress.Address.Bus = 0;
   PciAddress.Address.Device = 1;
   PciAddress.Address.Function = 0;
@@ -399,17 +399,17 @@ agesawrapper_getlateinitptr (
   }
 }
 
-UINT32 
+UINT32
 agesawrapper_amdinitmid (
   VOID
   )
 {
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
-  
+
   /* Enable MMIO on AMD CPU Address Map Controller */
   agesawrapper_amdinitcpuio ();
-  
+
   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),
@@ -431,7 +431,7 @@ agesawrapper_amdinitmid (
   return (UINT32)status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdinitlate (
   VOID
   )
@@ -467,10 +467,10 @@ agesawrapper_amdinitlate (
   return (UINT32)Status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdlaterunaptask (
-  UINT32 Func, 
-  UINT32 Data, 
+  UINT32 Func,
+  UINT32 Data,
   VOID *ConfigPtr
   )
 {
@@ -499,7 +499,7 @@ agesawrapper_amdlaterunaptask (
   return (UINT32)Status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdreadeventlog (
   VOID
   )
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.h b/src/mainboard/asrock/e350m1/agesawrapper.h
index 6d7d9cd196..21e43fe238 100644
--- a/src/mainboard/asrock/e350m1/agesawrapper.h
+++ b/src/mainboard/asrock/e350m1/agesawrapper.h
@@ -21,8 +21,8 @@
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */
- 
-  
+
+
 #ifndef _AGESAWRAPPER_H_
 #define _AGESAWRAPPER_H_
 
@@ -66,17 +66,17 @@ typedef struct {
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */
- 
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
- 
+
 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
- 
+
 UINT32 agesawrapper_amdinitreset (void);
 UINT32 agesawrapper_amdinitearly (void);
 UINT32 agesawrapper_amdinitenv (void);
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index cde9df7c5f..2707605b9b 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 /**
  * @file
  *
@@ -57,13 +57,13 @@
 #define INSTALL_FT1_SOCKET_SUPPORT  TRUE
 #define INSTALL_AM3_SOCKET_SUPPORT  FALSE
 
-/* 
- * Agesa optional capabilities selection.  
+/*
+ * Agesa optional capabilities selection.
  * Uncomment and mark FALSE those features you wish to include in the build.
  * Comment out or mark TRUE those features you want to REMOVE from the build.
  */
 
-#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE    
+#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_12_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_14_SUPPORT       FALSE
 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT       TRUE
@@ -104,7 +104,7 @@
 #define BLDOPT_REMOVE_HT_ASSIST         TRUE
 #define BLDOPT_REMOVE_ATM_MODE          TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE  
+//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
 #define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
@@ -125,10 +125,10 @@
 #define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
 #define AGESA_ENTRY_INIT_GENERAL_SERVICES         FALSE
 
-/* 
- * Agesa configuration values selection.  
+/*
+ * Agesa configuration values selection.
  * Uncomment and specify the value for the configuration options
- * needed by the system. 
+ * needed by the system.
  */
 
 /* The fixed MTRR values to be set after memory initialization. */
diff --git a/src/mainboard/asrock/e350m1/dimmSpd.c b/src/mainboard/asrock/e350m1/dimmSpd.c
index 8ef1b4c650..24e2617c0f 100644
--- a/src/mainboard/asrock/e350m1/dimmSpd.c
+++ b/src/mainboard/asrock/e350m1/dimmSpd.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"
@@ -55,7 +55,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
    UINT64 limit;
 
    address |= 1; // set read bit
-   
+
    __outbyte (iobase + 0, 0xFF);                // clear error status
    __outbyte (iobase + 1, 0x1F);                // clear error status
    __outbyte (iobase + 3, offset);              // offset in eeprom
@@ -112,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
  *
  * readspd - Read one or more SPD bytes from a DIMM.
  *           Start with offset zero and read sequentially.
- *           Optimization relies on autoincrement to avoid 
+ *           Optimization relies on autoincrement to avoid
  *           sending offset for every byte.
  *          Reads 128 bytes in 7-8 ms at 400 KHz.
  */
@@ -131,7 +131,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }
-   
+
    return 0;
    }
 
@@ -154,11 +154,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
    {
    int spdAddress, ioBase;
 
-   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR; 
-   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR; 
+   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
+   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;
    if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
-   
-   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; 
+
+   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
    if (spdAddress == 0) return AGESA_ERROR;
    ioBase = 0xB00;
    setupFch (ioBase);
diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c
index 43867172d5..9746248e87 100644
--- a/src/mainboard/asrock/e350m1/get_bus_conf.c
+++ b/src/mainboard/asrock/e350m1/get_bus_conf.c
@@ -68,22 +68,22 @@ void get_bus_conf(void)
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are 
- * written into RAM.  The routine that is responsible for writing the tables is 
- * "write_tables", called near the end of "hardwaremain".  There is no platform 
- * specific entry point between the S3 resume decision point and the call to 
- * "write_tables", and the next platform specific entry points are the calls to 
- * the ACPI table write functions.  The first of ose would seem to be the right 
- * place, but other table write functions, e.g. the PIRQ table write function, are 
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM.  The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions.  The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
-  status = agesawrapper_amdinitlate(); 
+  status = agesawrapper_amdinitlate();
   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }
-	
+
   sbdn_sb800 = 0;
 
   for (i = 0; i < 3; i++) {
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 397e82995a..960c2c86f1 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -60,11 +60,11 @@ static void *smp_write_config_table(void *v)
   mptable_write_buses(mc, NULL, &bus_isa);
 
   /* I/O APICs:   APIC ID Version State   Address */
-  
+
   device_t dev;
   u32 dword;
   u8 byte;
-    
+
   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
@@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v)
   /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
 
   /* on board NIC & Slot PCIE.  */
-  
+
   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
index f778243970..7fa4ee7404 100644
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -43,7 +43,7 @@ void enable_int_gfx(void)
 #ifdef UNUSED_CODE
 	RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
 	RWPMIO(SB_PMIOA_REGF6, AccWidthuint8, ~(BIT0), BIT0); /* Disable Gec */
-#endif	
+#endif
 	/* make sure the MMIO(fed80000) is accessible */
 	RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
 
diff --git a/src/mainboard/getac/p470/acpi_slic.c b/src/mainboard/getac/p470/acpi_slic.c
index 5744efad90..b042f36c7c 100644
--- a/src/mainboard/getac/p470/acpi_slic.c
+++ b/src/mainboard/getac/p470/acpi_slic.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c
index 46e7b886b1..676d6610be 100644
--- a/src/mainboard/getac/p470/acpi_tables.c
+++ b/src/mainboard/getac/p470/acpi_tables.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2010 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -87,7 +87,7 @@ static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
 
 static long acpi_create_ecdt(acpi_ecdt_t * ecdt)
 {
-	/* Attention: Make sure these match the values from 
+	/* Attention: Make sure these match the values from
 	 * the DSDT's ec.asl
 	 */
 	static const char ec_id[] = "\\_SB.PCI0.LPCB.EC0";
@@ -120,7 +120,7 @@ static long acpi_create_ecdt(acpi_ecdt_t * ecdt)
 	ecdt->ec_data.addrh = 0;
 
 	ecdt->uid = 1; // Must match _UID of the EC0 node.
-	
+
 	ecdt->gpe_bit = 23; // SCI interrupt within GPEx_STS
 
 	strncpy((char *)ecdt->ec_id, ec_id, strlen(ec_id));
@@ -260,7 +260,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	current += dsdt->length;
 	memcpy(dsdt, &AmlCode, dsdt->length);
 
-	/* Fix up global NVS region for SMI handler. The GNVS region lives 
+	/* Fix up global NVS region for SMI handler. The GNVS region lives
 	 * in the (high) table area. The low memory map looks like this:
 	 *
 	 * 0x00000000 - 0x000003ff	Real Mode IVT
@@ -313,7 +313,7 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	current += 0x100;
 	ALIGN_CURRENT;
-	
+
 	/* And tell SMI about it */
 	smm_setup_structures(gnvs, NULL, smi1);
 
diff --git a/src/mainboard/getac/p470/chip.h b/src/mainboard/getac/p470/chip.h
index db732d2876..b75c381e31 100644
--- a/src/mainboard/getac/p470/chip.h
+++ b/src/mainboard/getac/p470/chip.h
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
diff --git a/src/mainboard/getac/p470/ec_oem.c b/src/mainboard/getac/p470/ec_oem.c
index 30d41359cf..f742f3f72a 100644
--- a/src/mainboard/getac/p470/ec_oem.c
+++ b/src/mainboard/getac/p470/ec_oem.c
@@ -36,7 +36,7 @@ int send_ec_oem_command(u8 command)
 			printk(BIOS_SPEW, ".");
 	}
 	if (!timeout) {
-		printk(BIOS_DEBUG, "Timeout while sending OEM command 0x%02x to EC!\n", 
+		printk(BIOS_DEBUG, "Timeout while sending OEM command 0x%02x to EC!\n",
 				command);
 		// return -1;
 	}
@@ -124,7 +124,7 @@ int ec_oem_dump_status(void)
 	if (ec_sc & (1 << 1)) printk(BIOS_DEBUG, "IBF ");
 	if (ec_sc & (1 << 0)) printk(BIOS_DEBUG, "OBF ");
 	printk(BIOS_DEBUG, "\n");
-	
+
 	return ec_sc;
 }
 
diff --git a/src/mainboard/getac/p470/hda_verb.h b/src/mainboard/getac/p470/hda_verb.h
index 0edd0f3607..98a77c6e12 100644
--- a/src/mainboard/getac/p470/hda_verb.h
+++ b/src/mainboard/getac/p470/hda_verb.h
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c
index 8f8a39544c..b7a248dbfd 100644
--- a/src/mainboard/getac/p470/mainboard.c
+++ b/src/mainboard/getac/p470/mainboard.c
@@ -32,7 +32,7 @@
 
 #define MAX_LCD_BRIGHTNESS	0xd8
 
-static void ec_enable(void) 
+static void ec_enable(void)
 {
 	u16 keymap;
 	/* Enable Hotkey SCI */
@@ -59,11 +59,11 @@ static void pcie_limit_power(void)
 {
 #if 0
 	// This piece of code needs further debugging as it crashes the
-	// machine. It should set the slot numbers and enable power 
+	// machine. It should set the slot numbers and enable power
 	// limitation for the PCIe slots.
 
 	device_t dev;
-	
+
 	dev = dev_find_slot(0, PCI_DEVFN(28,0));
 	if (dev) pci_write_config32(dev, 0x54, 0x0010a0e0);
 
@@ -89,9 +89,9 @@ static void mainboard_init(device_t dev)
 	ec_enable();
 }
 
-// mainboard_enable is executed as first thing after 
+// mainboard_enable is executed as first thing after
 // enumerate_buses(). Is there no mainboard_init()?
-static void mainboard_enable(device_t dev) 
+static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	pcie_limit_power();
diff --git a/src/mainboard/getac/p470/mainboard_smi.c b/src/mainboard/getac/p470/mainboard_smi.c
index d29fe587c8..4a5a3ffbbb 100644
--- a/src/mainboard/getac/p470/mainboard_smi.c
+++ b/src/mainboard/getac/p470/mainboard_smi.c
@@ -30,7 +30,7 @@
 
 #define MAX_LCD_BRIGHTNESS 0xd8
 
-/* The southbridge SMI handler checks whether gnvs has a 
+/* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler
  */
 extern global_nvs_t *gnvs;
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 6fa2620257..afad4bc820 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -320,7 +320,7 @@ void main(unsigned long bist)
 
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
-	
+
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 	dump_spd_registers();
 #endif
@@ -330,8 +330,8 @@ void main(unsigned long bist)
 	/* Perform some initialization that must run before stage2 */
 	early_ich7_init();
 
-	/* This should probably go away. Until now it is required 
-	 * and mainboard specific 
+	/* This should probably go away. Until now it is required
+	 * and mainboard specific
 	 */
 	rcba_config();
 
@@ -373,7 +373,7 @@ void main(unsigned long bist)
 		 * memory completely, but that's a wonderful clean up task for another
 		 * day.
 		 */
-		if (resume_backup_memory) 
+		if (resume_backup_memory)
 			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 
 		/* Magic for S3 resume */
diff --git a/src/mainboard/getac/p470/rtl8168.c b/src/mainboard/getac/p470/rtl8168.c
index f0f98d20f4..37ef674362 100644
--- a/src/mainboard/getac/p470/rtl8168.c
+++ b/src/mainboard/getac/p470/rtl8168.c
@@ -29,7 +29,7 @@
 static void nic_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n");
-	// Nothing to do yet, but this has to be here to keep 
+	// Nothing to do yet, but this has to be here to keep
 	// coreboot from trying to execute an option ROM.
 
 #ifdef RTL8168_DEBUG
diff --git a/src/mainboard/gigabyte/m57sli/mainboard.c b/src/mainboard/gigabyte/m57sli/mainboard.c
index 3b7eb7d49f..b198fb67c5 100644
--- a/src/mainboard/gigabyte/m57sli/mainboard.c
+++ b/src/mainboard/gigabyte/m57sli/mainboard.c
@@ -34,7 +34,7 @@ static void verb_setup(void)
 	// cim_verb_data_size = sizeof(mainboard_cim_verb_data);
 }
 
-static void mainboard_enable(device_t dev) 
+static void mainboard_enable(device_t dev)
 {
 	verb_setup();
 }
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index d40df6b95d..32a94d425b 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -105,7 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	struct sys_info *sysinfo =  (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 	u32 bsp_apicid = 0, val;
 	msr_t msr;
- 
+
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */
 		/* Allow the HT devices to be found */
diff --git a/src/mainboard/msi/ms9282/mainboard.c b/src/mainboard/msi/ms9282/mainboard.c
index bbb1024bf7..99f7e224d1 100644
--- a/src/mainboard/msi/ms9282/mainboard.c
+++ b/src/mainboard/msi/ms9282/mainboard.c
@@ -34,7 +34,7 @@ static void verb_setup(void)
 	// cim_verb_data_size = sizeof(mainboard_cim_verb_data);
 }
 
-static void mainboard_enable(device_t dev) 
+static void mainboard_enable(device_t dev)
 {
 	verb_setup();
 }
diff --git a/src/mainboard/msi/ms9652_fam10/mainboard.c b/src/mainboard/msi/ms9652_fam10/mainboard.c
index af793c7f9c..255b22d74f 100644
--- a/src/mainboard/msi/ms9652_fam10/mainboard.c
+++ b/src/mainboard/msi/ms9652_fam10/mainboard.c
@@ -34,7 +34,7 @@ static void verb_setup(void)
 	// cim_verb_data_size = sizeof(mainboard_cim_verb_data);
 }
 
-static void mainboard_enable(device_t dev) 
+static void mainboard_enable(device_t dev)
 {
 	verb_setup();
 }
diff --git a/src/mainboard/nvidia/l1_2pvv/hda_verb.h b/src/mainboard/nvidia/l1_2pvv/hda_verb.h
index 0b7aac8566..054a3699bc 100644
--- a/src/mainboard/nvidia/l1_2pvv/hda_verb.h
+++ b/src/mainboard/nvidia/l1_2pvv/hda_verb.h
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2004 Tyan Computer
  * Copyright (C) 2006-2007 AMD
  * Copyright (C) 2007-2009 coresystems GmbH
diff --git a/src/mainboard/nvidia/l1_2pvv/mainboard.c b/src/mainboard/nvidia/l1_2pvv/mainboard.c
index 4c6f0c0290..b425c3d80f 100644
--- a/src/mainboard/nvidia/l1_2pvv/mainboard.c
+++ b/src/mainboard/nvidia/l1_2pvv/mainboard.c
@@ -33,7 +33,7 @@ static void verb_setup(void)
 	cim_verb_data_size = sizeof(mainboard_cim_verb_data);
 }
 
-static void mainboard_enable(device_t dev) 
+static void mainboard_enable(device_t dev)
 {
 	verb_setup();
 }
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
index fd731f9e79..b79372aee7 100644
--- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
+++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
@@ -128,13 +128,13 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	struct resource *res;
 	resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default
-	
+
 	device_t dev = dev_find_slot(0,PCI_DEVFN(0,0));
 	// we report mmconf base
 	res = probe_resource(dev, 0x1C);
 	if( res )
 		mmconf_base = res->base;
-		
+
 	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ?
 
 	return current;
@@ -180,7 +180,7 @@ unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
 	int i;
-	
+
 	acpi_rsdp_t *rsdp;
 	acpi_rsdt_t *rsdt;
 	acpi_srat_t *srat;
@@ -192,7 +192,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
-	
+
 	get_bus_conf();		/* it will get sblk, pci1234, hcdn, and sbdn */
 
 	/* Align ACPI tables to 16byte */
@@ -204,14 +204,14 @@ unsigned long write_acpi_tables(unsigned long start)
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (acpi_rsdp_t *) current;
 	current += sizeof(acpi_rsdp_t);
-	ALIGN_CURRENT;	
+	ALIGN_CURRENT;
 	rsdt = (acpi_rsdt_t *) current;
 	current += sizeof(acpi_rsdt_t);
 	ALIGN_CURRENT;
 	xsdt = (acpi_xsdt_t *) current;
 	current += sizeof(acpi_xsdt_t);
 	ALIGN_CURRENT;
-	
+
 	/* clear all table memory */
 	memset((void *)start, 0, current - start);
 
@@ -234,7 +234,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_create_my_hpet(hpet);
 	current += sizeof(acpi_hpet_t);
 	acpi_add_table(rsdp, hpet);
-	
+
 	/* If we want to use HPET Timers Linux wants an MADT */
 	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
@@ -247,15 +247,15 @@ unsigned long write_acpi_tables(unsigned long start)
 	mcfg = (acpi_mcfg_t *) current;
 	acpi_create_mcfg(mcfg);
 	current += mcfg->header.length;
-	acpi_add_table(rsdp, mcfg);	
-	
+	acpi_add_table(rsdp, mcfg);
+
 	/* SSDT */
 	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
 	current += ssdt->length;
-	acpi_add_table(rsdp, ssdt);	
-	
+	acpi_add_table(rsdp, ssdt);
+
 	/* DSDT */
 	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
 	dsdt = (acpi_header_t *)current;
@@ -267,7 +267,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	for (i=0; i < dsdt->length; i++) {
 		if (*(u32*)(((u32)dsdt) + i) == 0xBADEAFFE) {
 			printk(BIOS_DEBUG, "ACPI: Patching up globals in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
-			*(u32*)(((u32)dsdt) + i) = current; 
+			*(u32*)(((u32)dsdt) + i) = current;
 			break;
 		}
 	}
@@ -277,8 +277,8 @@ unsigned long write_acpi_tables(unsigned long start)
 	current += GLOBAL_VARS_SIZE;
 	/* We patched up the DSDT, so we need to recalculate the checksum */
 	dsdt->checksum = 0;
-	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);	
-	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);	
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
 
 	/* FADT */
 	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
diff --git a/src/mainboard/siemens/sitemp_g1p1/int15_func.c b/src/mainboard/siemens/sitemp_g1p1/int15_func.c
index 0d2da370ff..c6531913ae 100644
--- a/src/mainboard/siemens/sitemp_g1p1/int15_func.c
+++ b/src/mainboard/siemens/sitemp_g1p1/int15_func.c
@@ -20,7 +20,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #include <stdint.h>
 #include <stdlib.h>
 #include <console/console.h>
@@ -80,7 +80,7 @@ int sbios_INT15_handler(struct eregs *regs)
 			regs->eax &= ~(0xff);
 			regs->ebx &= ~(0xff);
 			printk(BIOS_DEBUG, "Integrated System Information = %x:%x\n", regs->edx, regs->edi);
-			vgainfo_addr = (regs->edx * 16) + regs->edi; 
+			vgainfo_addr = (regs->edx * 16) + regs->edi;
 			res = 0;
 			break;
 		case 0x89:
diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
index 2b726f9b17..60a2ee2188 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
@@ -4,7 +4,7 @@
  * Copyright (C) 2008 Advanced Micro Devices, Inc.
  * Copyright (C) 2010 Siemens AG, Inc.
  * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -18,7 +18,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -172,7 +172,7 @@ static u32 adt7475_address = ADT7475_ADDRESS;
 
 #define adt7475_write_byte(reg, val) \
 	do_smbus_write_byte(smbus_io_base, adt7475_address, reg, val)
-	
+
 #define TWOS_COMPL 1
 
 struct __table__{
@@ -284,9 +284,9 @@ static void int15_install(void)
 /* ############################################################################################# */
 
  /**
- * @brief 
+ * @brief
  *
- * @param 
+ * @param
  */
 
 static u8 calc_trange(u8 t_min, u8 t_max) {
@@ -294,7 +294,7 @@ static u8 calc_trange(u8 t_min, u8 t_max) {
 	u8 prev;
 	int i;
 	int diff = t_max - t_min;
-	
+
 	// walk through the trange table
 	for(i = 0, prev = 0; i < sizeof(trange)/sizeof(int); i++) {
 		if( trange[i] < diff ) {
@@ -304,7 +304,7 @@ static u8 calc_trange(u8 t_min, u8 t_max) {
 		if( diff == trange[i] ) return i;
 		if( (diff - trange[prev]) < (trange[i] - diff) ) break; // return with last val index
 		return i;
-	}		
+	}
 	return prev;
 }
 
@@ -319,7 +319,7 @@ static void cable_detect(void)
 	u8 byte;
 	struct device *sm_dev;
 	struct device *ide_dev;
-	
+
 	/* SMBus Module and ACPI Block (Device 20, Function 0) on SB600 */
 	printk(BIOS_DEBUG, "%s.\n", __func__);
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -327,7 +327,7 @@ static void cable_detect(void)
 	byte = pci_read_config8(sm_dev, 0xA9);
 	byte |= (1 << 5);	/* Set Gpio9 as input */
 	pci_write_config8(sm_dev, 0xA9, byte);
-	
+
 	/* IDE Controller (Device 20, Function 1) on SB600 */
 	ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
 
@@ -347,14 +347,14 @@ static void cable_detect(void)
 /**
  * @brief Detect the ADT7475 device
  *
- * @param 
+ * @param
  */
- 
+
 static const char * adt7475_detect( void ) {
 
         int vendid, devid, devid2;
         const char *name = NULL;
-		
+
         vendid = adt7475_read_byte(REG_VENDID);
         devid2 = adt7475_read_byte(REG_DEVID2);
         if (vendid != 0x41 ||           /* Analog Devices */
@@ -371,7 +371,7 @@ static const char * adt7475_detect( void ) {
                 name = "adt7476";
         else if ((devid2 & 0xfc) == 0x6c)
                 name = "adt7490";
- 
+
         return name;
 }
 
@@ -396,7 +396,7 @@ const struct fan_control case_fan_control_defaults = {
 static void pm_init( void )
 {
 	u16 word;
-	u8 byte; 
+	u8 byte;
 	device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
 	/* set SB600 GPIO 64 to GPIO with pull-up */
@@ -423,7 +423,7 @@ static void pm_init( void )
 	byte = pm_ioread(0x3c);
 	byte &= 0xf3;
 	pm_iowrite(0x3c, byte);
-	
+
 	/* set GPM5 to not wake from s5 */
 	byte = pm_ioread(0x77);
 	byte &= ~(1 << 5);
@@ -433,7 +433,7 @@ static void pm_init( void )
  /**
  * @brief Setup thermal config on SINA Mainboard
  *
- * @param 
+ * @param
  */
 
 static void set_thermal_config(void)
@@ -443,17 +443,17 @@ static void set_thermal_config(void)
 	device_t sm_dev;
 	struct fan_control cpu_fan_control, case_fan_control;
 	const char *name = NULL;
-	
-		
+
+
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 	smbus_io_base = pci_read_config32(sm_dev, 0x10) & ~(0xf); // get BAR0-Address which holds the SMBUS_IO_BASE
-	
+
 	if( (name = adt7475_detect()) == NULL ) {
 		printk(BIOS_NOTICE, "Couldn't detect an ADT7473/75/76/90 part at %x:%x\n", smbus_io_base, adt7475_address);
 		return;
 	}
 	printk(BIOS_DEBUG, "Found %s part at %x:%x\n", name, smbus_io_base, adt7475_address);
-	
+
 	cpu_fan_control = cpu_fan_control_defaults;
 	case_fan_control = case_fan_control_defaults;
 
@@ -463,7 +463,7 @@ static void set_thermal_config(void)
 		// get all the options needed
 		if( get_option(&byte, "cpu_fan_control") == 0 )
 			cpu_fan_control.enable = byte ? 1 : 0;
-			
+
 		get_option(&cpu_fan_control.polarity, "cpu_fan_polarity");
 		get_option(&cpu_fan_control.t_min, "cpu_t_min");
 		get_option(&cpu_fan_control.t_max, "cpu_t_max");
@@ -471,13 +471,13 @@ static void set_thermal_config(void)
 		get_option(&cpu_fan_control.pwm_max, "cpu_dutycycle_max");
 
 		if( get_option(&byte, "chassis_fan_control") == 0)
-			case_fan_control.enable = byte ? 1 : 0;		
-		get_option(&case_fan_control.polarity, "chassis_fan_polarity");	
+			case_fan_control.enable = byte ? 1 : 0;
+		get_option(&case_fan_control.polarity, "chassis_fan_polarity");
 		get_option(&case_fan_control.t_min, "chassis_t_min");
 		get_option(&case_fan_control.t_max, "chassis_t_max");
 		get_option(&case_fan_control.pwm_min, "chassis_dutycycle_min");
 		get_option(&case_fan_control.pwm_max, "chassis_dutycycle_max");
-	
+
 	}
 
 	printk(BIOS_DEBUG, "cpu_fan_control:%s", cpu_fan_control.enable ? "enable" : "disable");
@@ -485,50 +485,50 @@ static void set_thermal_config(void)
 
 	printk(BIOS_DEBUG, " cpu_t_min:%s", TEMPERATURE_INFO(cpu_fan_control.t_min));
 	cpu_fan_control.t_min = TEMPERATURE(cpu_fan_control.t_min, cpu_fan_control_defaults.t_min);
-	
+
 	printk(BIOS_DEBUG, " cpu_t_max:%s", TEMPERATURE_INFO(cpu_fan_control.t_max));
 	cpu_fan_control.t_max = TEMPERATURE(cpu_fan_control.t_max, cpu_fan_control_defaults.t_max);
-	
+
 	printk(BIOS_DEBUG, " cpu_pwm_min:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_min));
 	cpu_fan_control.pwm_min = DUTYCYCLE(cpu_fan_control.pwm_min, cpu_fan_control_defaults.pwm_min);
-	
+
 	printk(BIOS_DEBUG, " cpu_pwm_max:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_max));
 	cpu_fan_control.pwm_max = DUTYCYCLE(cpu_fan_control.pwm_max, cpu_fan_control_defaults.pwm_max);
-	
+
 	cpu_fan_control.t_range = calc_trange(cpu_fan_control.t_min, cpu_fan_control.t_max);
 	printk(BIOS_DEBUG, " cpu_t_range:0x%02x\n", cpu_fan_control.t_range);
 	cpu_fan_control.t_range <<= 4;
 	cpu_fan_control.t_range |= (4 << 0); // 35.3Hz
-	
+
 	printk(BIOS_DEBUG, "chassis_fan_control:%s", case_fan_control.enable ? "enable" : "disable");
 	printk(BIOS_DEBUG, " chassis_fan_polarity:%s", case_fan_control.polarity ? "low" : "high");
 
 	printk(BIOS_DEBUG, " chassis_t_min:%s", TEMPERATURE_INFO(case_fan_control.t_min));
 	case_fan_control.t_min = TEMPERATURE(case_fan_control.t_min, case_fan_control_defaults.t_min);
-	
+
 	printk(BIOS_DEBUG, " chassis_t_max:%s", TEMPERATURE_INFO(case_fan_control.t_max));
 	case_fan_control.t_max = TEMPERATURE(case_fan_control.t_max, case_fan_control_defaults.t_max);
-	
+
 	printk(BIOS_DEBUG, " chassis_pwm_min:%s", DUTYCYCLE_INFO(case_fan_control.pwm_min));
 	case_fan_control.pwm_min = DUTYCYCLE(case_fan_control.pwm_min, case_fan_control_defaults.pwm_min);
-	
+
 	printk(BIOS_DEBUG, " chassis_pwm_max:%s", DUTYCYCLE_INFO(case_fan_control.pwm_max));
 	case_fan_control.pwm_max = DUTYCYCLE(case_fan_control.pwm_max, case_fan_control_defaults.pwm_max);
-	
+
 	case_fan_control.t_range = calc_trange(case_fan_control.t_min, case_fan_control.t_max);
 	printk(BIOS_DEBUG, " case_t_range:0x%02x\n", case_fan_control.t_range);
 	case_fan_control.t_range <<= 4;
 	case_fan_control.t_range |= (4 << 0); // 35.3Hz
-	
+
 	cpu_pwm_conf = (((cpu_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
 	case_pwm_conf = (((case_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
-	cpu_pwm_conf |= cpu_fan_control.enable ? (0 << 5) : (7 << 5);  // manual control 
+	cpu_pwm_conf |= cpu_fan_control.enable ? (0 << 5) : (7 << 5);  // manual control
 	case_pwm_conf |= case_fan_control.enable ? (1 << 5) : (7 << 5); // local temp
-	
+
 	/* set adt7475 */
 
 	adt7475_write_byte(REG_CONFIG1, 0x04);  // clear register, bit 2 is read only
-	
+
 	/* Config Register 6:  */
 	adt7475_write_byte(REG_CONFIG6, 0x00);
 	/* Config Register 7 */
@@ -536,14 +536,14 @@ static void set_thermal_config(void)
 
 	/* Config Register 5: */
 	/* set Offset 64 format, enable THERM on Remote 1& Local */
-	adt7475_write_byte(REG_CONFIG5, TWOS_COMPL ? 0x61 : 0x60); 
+	adt7475_write_byte(REG_CONFIG5, TWOS_COMPL ? 0x61 : 0x60);
 	/* No offset for remote 1 */
 	adt7475_write_byte(TEMP_OFFSET_REG(0), 0x00);
 	/* No offset for local */
 	adt7475_write_byte(TEMP_OFFSET_REG(1), 0x00);
 	/* No offset for remote 2 */
 	adt7475_write_byte(TEMP_OFFSET_REG(2), 0x00);
-	
+
 	/* remote 1 low temp limit */
 	adt7475_write_byte(TEMP_MIN_REG(0), 0x00);
 	/* remote 1 High temp limit    (90C) */
@@ -558,7 +558,7 @@ static void set_thermal_config(void)
 	adt7475_write_byte(TEMP_THERM_REG(0), 0x9f);
 	/* local therm temp limit    (95C) */
 	adt7475_write_byte(TEMP_THERM_REG(1), 0x9f);
-	
+
 	/* PWM 1 configuration register    CPU fan controlled by CPU Thermal Diode */
 	adt7475_write_byte(PWM_CONFIG_REG(0), cpu_pwm_conf);
 	/* PWM 3 configuration register    Case fan controlled by ADTxxxx temp */
@@ -576,7 +576,7 @@ static void set_thermal_config(void)
 	} else {
 		adt7475_write_byte(PWM_REG(0), cpu_fan_control.pwm_max);
 	}
-	
+
 	if( case_fan_control.enable ) {
 		/* PWM 2 minimum duty cycle     (37%) */
 		adt7475_write_byte(PWM_MIN_REG(2), case_fan_control.pwm_min);
@@ -597,10 +597,10 @@ static void set_thermal_config(void)
 	adt7475_write_byte(0x7d, 0x09);
 	/* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 3 fault, SmbAlert Fan for Therm Timer event */
 	adt7475_write_byte(0x75, 0x2e);
-	
+
 	/* Config Register 1 Set Start bit */
 	adt7475_write_byte(0x40, 0x05);
-	
+
 	/* Read status register to clear any old errors */
 	byte2 = adt7475_read_byte(0x42);
 	byte = adt7475_read_byte(0x41);
@@ -611,20 +611,20 @@ static void set_thermal_config(void)
 }
 
  /**
- * @brief 
+ * @brief
  *
- * @param 
+ * @param
  */
 
 static void patch_mmio_nonposted( void )
 {
-	unsigned reg, index;		
+	unsigned reg, index;
 	resource_t rbase, rend;
 	u32 base, limit;
 	struct resource *resource;
 	device_t dev;
 	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1));
-	
+
 	printk(BIOS_DEBUG,"%s ...\n", __func__);
 
 	dev = dev_find_slot(1, PCI_DEVFN(5,0));
@@ -637,7 +637,7 @@ static void patch_mmio_nonposted( void )
 		rbase = (resource->base >> 8) & ~(0xff);
 		/* Get the limit (rounded up) */
 		rend  = (resource_end(resource) >> 8) & ~(0xff);
-	
+
 		printk(BIOS_DEBUG,"%s %x base = %0llx limit = %0llx\n", dev_path(dev), index, rbase, rend);
 
 		for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
@@ -645,9 +645,9 @@ static void patch_mmio_nonposted( void )
 			limit = pci_read_config32(k8_f1,reg+4);
 			printk(BIOS_DEBUG," %02x[%08x] %02x[%08x]", reg, base, reg+4, limit);
 			if( ((base & ~(0xff)) == rbase) && ((limit & ~(0xff)) == rend) ) {
-				limit |= (1 << 7); 
+				limit |= (1 << 7);
 				printk(BIOS_DEBUG, "\nPatching %s %x <- %08x", dev_path(k8_f1), reg, limit);
-				pci_write_config32(k8_f1, reg+4, limit); 
+				pci_write_config32(k8_f1, reg+4, limit);
 				break;
 			}
 		}
@@ -656,22 +656,22 @@ static void patch_mmio_nonposted( void )
 }
 
  /**
- * @brief 
+ * @brief
  *
- * @param 
+ * @param
  */
- 
+
 static void wait_pepp( void ) {
 
 	int boot_delay = 0;
-	
+
 	if( get_option(&boot_delay, "boot_delay") < 0)
 		boot_delay = 5;
-		
+
 	printk(BIOS_DEBUG, "boot_delay = %d sec\n", boot_delay);
 	if ( boot_delay > 0 ) {
 		init_timer();
-		// wait for PEPP-Board 
+		// wait for PEPP-Board
 		printk(BIOS_INFO, "Give PEPP-Board %d sec(s) time to coming up ", boot_delay);
 		while ( boot_delay ) {
 			lapic_write(LAPIC_TMICT, 0xffffffff);
@@ -684,9 +684,9 @@ static void wait_pepp( void ) {
 }
 
  /**
- * @brief 
+ * @brief
  *
- * @param 
+ * @param
  */
 
 struct {
@@ -700,13 +700,13 @@ struct {
 	{0, PCI_DEVFN(5,0)},{0, PCI_DEVFN(5,2)},
 	{255,0},
 };
- 
+
 
 static void update_subsystemid( device_t dev ) {
 
 	int i;
 	struct mainboard_config *mb = dev->chip_info;
-	
+
 	dev->subsystem_vendor = 0x110a;
 	if( mb->plx_present ){
 		dev->subsystem_device = 0x4076; // U1P1 = 0x4076, U1P0 = 0x4077
@@ -725,9 +725,9 @@ static void update_subsystemid( device_t dev ) {
 }
 
  /**
- * @brief 
+ * @brief
  *
- * @param 
+ * @param
  */
 
 static void detect_hw_variant( device_t dev ) {
@@ -736,7 +736,7 @@ static void detect_hw_variant( device_t dev ) {
 	struct southbridge_amd_rs690_config *cfg;
 	u32 lc_state, id = 0;
 	struct mainboard_config *mb = dev->chip_info;
-	
+
 	printk(BIOS_INFO, "Scan for PLX device ...\n");
 	nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 	if (!nb_dev) {
@@ -769,19 +769,19 @@ static void detect_hw_variant( device_t dev ) {
 		struct device dummy;
 		u32 pci_primary_bus, buses;
 		u16 secondary, subordinate;
-		
-		printk(BIOS_DEBUG, "Scan for PLX bridge behind %s[%x]\n", dev_path(dev2), pci_read_config32(dev2, PCI_VENDOR_ID));		
+
+		printk(BIOS_DEBUG, "Scan for PLX bridge behind %s[%x]\n", dev_path(dev2), pci_read_config32(dev2, PCI_VENDOR_ID));
 		// save the existing primary/secondary/subordinate bus number configuration.
 		secondary = dev2->bus->secondary;
 		subordinate = dev2->bus->subordinate;
 		buses = pci_primary_bus = pci_read_config32(dev2, PCI_PRIMARY_BUS);
 
 		// Configure the bus numbers for this bridge
-		// bus number 1 is for internal gfx device, so we start with busnumber 2 
+		// bus number 1 is for internal gfx device, so we start with busnumber 2
 
 		buses &= 0xff000000;
 		buses |= ((2 << 8) | (0xff << 16));
-		// setup the buses in device 2		
+		// setup the buses in device 2
 		pci_write_config32(dev2,PCI_PRIMARY_BUS, buses);
 
 		// fake a device descriptor for a device behind device 2
@@ -795,7 +795,7 @@ static void detect_hw_variant( device_t dev ) {
 		/* Have we found something?
 		 * Some broken boards return 0 if a slot is empty, but
 		 * the expected answer is 0xffffffff
-		 */	
+		 */
 		if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) {
 			printk(BIOS_DEBUG, "%s, bad id 0x%x\n", dev_path(&dummy), id);
 		} else {
@@ -810,8 +810,8 @@ static void detect_hw_variant( device_t dev ) {
 	default:
 		break;
 	}
-	
-	mb->plx_present = 0;	
+
+	mb->plx_present = 0;
 	if( id == PLX_VIDDID ){
 		printk(BIOS_INFO, "found PLX device\n");
 		mb->plx_present = 1;
@@ -822,7 +822,7 @@ static void detect_hw_variant( device_t dev ) {
 			cfg->gfx_link_width = 4;
 		}
 		return;
-	} 
+	}
 }
 
 static void smm_lock( void )
@@ -841,16 +841,16 @@ static void smm_lock( void )
  *
  * @param the root device
  */
- 
+
 static void init(device_t dev)
 {
 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0
 	INT15_function_extensions int15_func;
 #endif
-	
+
 	printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n",
 		dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
-	
+
 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0
 	if(	get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") < 0 )
 		int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO;
@@ -870,7 +870,7 @@ static void init(device_t dev)
 *************************************************/
 static void enable_dev(device_t dev)
 {
-	
+
 	printk(BIOS_INFO, "%s %s[%x/%x] %s\n",
 		dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
@@ -880,19 +880,19 @@ static void enable_dev(device_t dev)
 
 	detect_hw_variant(dev);
 	update_subsystemid(dev);
-	
+
 #if (CONFIG_GFXUMA == 1)
 	{
 	msr_t msr, msr2;
-	
+
 	/* TOP_MEM: the top of DRAM below 4G */
 	msr = rdmsr(TOP_MEM);
 	printk(BIOS_DEBUG, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
 		    __func__, msr.lo, msr.hi);
-	
+
 	/* TOP_MEM2: the top of DRAM above 4G */
 	msr2 = rdmsr(TOP_MEM2);
-	
+
 	printk(BIOS_DEBUG, "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
 		    __func__, msr2.lo, msr2.hi);
 
@@ -915,7 +915,7 @@ static void enable_dev(device_t dev)
 	}
 
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
-	
+
 	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
 		    __func__, uma_memory_size, uma_memory_base);
 
@@ -927,20 +927,20 @@ static void enable_dev(device_t dev)
 #endif
 
 	wait_pepp();
-	dev->ops->init = init;  // rest of mainboard init later   
+	dev->ops->init = init;  // rest of mainboard init later
 }
 
  /**
- * @brief 
+ * @brief
  *
- * @param 
+ * @param
  */
 
 int add_mainboard_resources(struct lb_memory *mem)
 {
 	device_t dev;
 	struct resource *res;
-	
+
 	dev = dev_find_slot(0, PCI_DEVFN(0,0));
 	res = probe_resource(dev, 0x1C);
 	if( res ) {
diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index 9e4a6db028..ba2c1e4c1c 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
 	int isa_bus;
-	
+
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	mptable_init(mc, LAPIC_ADDR);
 	smp_write_processors(mc);
diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c
index 09aa1d7f45..b570d4581d 100644
--- a/src/mainboard/siemens/sitemp_g1p1/romstage.c
+++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c
@@ -18,7 +18,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
@@ -177,7 +177,7 @@ static inline void check_cmos( void ) {
 			outb(0x0a,0x72);
 			i = inb(0x73);
 			i &= ~(1 << 4);
-			outb(i,0x73);					
+			outb(i,0x73);
 
 			for (i = 14; i < 128; i++) {
 #if DUMP_CMOS_RAM
@@ -198,7 +198,7 @@ static inline void check_cmos( void ) {
 			/* Now reboot to run with default cmos. */
 			outb(0x06, 0xcf9);
 			for (;;) asm("hlt"); /* Wait for reset! */
-		} 
+		}
 	}
 
 	// update altcentury
@@ -221,7 +221,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	msr_t msr;
 	struct cpuid_result cpuid1;
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-			
+
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */
 		/* Allow the HT devices to be found */
@@ -237,19 +237,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	enable_rs690_dev8(); // enable CFG access to Dev8, which is the SB P2P Bridge
 	sb600_lpc_init();
-#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0)	
-	check_cmos();  // rebooting in case of corrupted cmos !!!!!	
-#endif	
+#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0)
+	check_cmos();  // rebooting in case of corrupted cmos !!!!!
+#endif
 	/* it8712f_enable_serial does not use its 1st parameter. */
 	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
-	it8712f_kill_watchdog(); 
+	it8712f_kill_watchdog();
 
 	console_init();
 #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1)
-	check_cmos();  // rebooting in case of corrupted cmos !!!!!		
+	check_cmos();  // rebooting in case of corrupted cmos !!!!!
 #endif
 	post_code(0x03);
-	
+
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 	__DEBUG__("bsp_apicid=0x%x\n", bsp_apicid);
@@ -270,9 +270,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* run _early_setup before soft-reset. */
 	rs690_early_setup();
 	sb600_early_setup();
-	
+
 	post_code(0x04);
-	
+
 	/* Check to see if processor is capable of changing FIDVID  */
 	/* otherwise it will throw a GP# when reading FIDVID_STATUS */
 	cpuid1 = cpuid(0x80000007);
@@ -293,16 +293,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	} else {
 		__DEBUG__("Changing FIDVID not supported\n");
 	}
-	
+
 	post_code(0x05);
-	
+
 	needs_reset = optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 	rs690_htinit();
 	__DEBUG__("needs_reset=0x%x\n", needs_reset);
-	
+
 	post_code(0x06);
-	
+
 	if (needs_reset) {
 		__INFO__("ht reset -\n");
 		soft_reset();
@@ -314,19 +314,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	__DEBUG__("sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 		     sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-	
+
 	post_code(0x07);
-	
+
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-	
+
 	post_code(0x08);
-	
+
 	rs690_before_pci_init(); // does nothing
 	sb600_before_pci_init();
-	
-#if CONFIG_USE_OPTION_TABLE	
+
+#if CONFIG_USE_OPTION_TABLE
 	if( read_option(cmos_defaults_loaded, 0) )
-		__WARNING__("WARNING: CMOS DEFAULTS LOADED. PLEASE CHECK CMOS OPTION \"cmos_default_loaded\" !\n"); 
+		__WARNING__("WARNING: CMOS DEFAULTS LOADED. PLEASE CHECK CMOS OPTION \"cmos_default_loaded\" !\n");
 #endif
 
 	post_cache_as_ram();
diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
index b7f0124034..b7f0124034 100755..100644
--- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
+++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
index 24a05fb868..24a05fb868 100755..100644
--- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
+++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h
index eb756df9b3..eb756df9b3 100755..100644
--- a/src/mainboard/supermicro/h8qgi/OptionsIds.h
+++ b/src/mainboard/supermicro/h8qgi/OptionsIds.h
diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c
index b8ce0b0431..b8ce0b0431 100755..100644
--- a/src/mainboard/supermicro/h8qgi/acpi_tables.c
+++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c
index 5bb4a9db5d..5bb4a9db5d 100755..100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.c
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.h b/src/mainboard/supermicro/h8qgi/agesawrapper.h
index 43c7d10d90..43c7d10d90 100755..100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.h
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.h
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
index 02cf79b8cf..02cf79b8cf 100755..100644
--- a/src/mainboard/supermicro/h8qgi/buildOpts.c
+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c
diff --git a/src/mainboard/supermicro/h8qgi/chip.h b/src/mainboard/supermicro/h8qgi/chip.h
index a252705293..a252705293 100755..100644
--- a/src/mainboard/supermicro/h8qgi/chip.h
+++ b/src/mainboard/supermicro/h8qgi/chip.h
diff --git a/src/mainboard/supermicro/h8qgi/dimmSpd.c b/src/mainboard/supermicro/h8qgi/dimmSpd.c
index 4ff21ee3ca..4ff21ee3ca 100755..100644
--- a/src/mainboard/supermicro/h8qgi/dimmSpd.c
+++ b/src/mainboard/supermicro/h8qgi/dimmSpd.c
diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c
index c2f714dfaf..c2f714dfaf 100755..100644
--- a/src/mainboard/supermicro/h8qgi/fadt.c
+++ b/src/mainboard/supermicro/h8qgi/fadt.c
diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
index 14e6bca2cd..14e6bca2cd 100755..100644
--- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c
index 640a0a60a0..640a0a60a0 100755..100644
--- a/src/mainboard/supermicro/h8qgi/irq_tables.c
+++ b/src/mainboard/supermicro/h8qgi/irq_tables.c
diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c
index f00b5a048f..f00b5a048f 100755..100644
--- a/src/mainboard/supermicro/h8qgi/mainboard.c
+++ b/src/mainboard/supermicro/h8qgi/mainboard.c
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 7373cb8a18..7373cb8a18 100755..100644
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.c b/src/mainboard/supermicro/h8qgi/platform_oem.c
index f36b0d83b8..f36b0d83b8 100755..100644
--- a/src/mainboard/supermicro/h8qgi/platform_oem.c
+++ b/src/mainboard/supermicro/h8qgi/platform_oem.c
diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.h b/src/mainboard/supermicro/h8qgi/platform_oem.h
index ab0d6df332..ab0d6df332 100755..100644
--- a/src/mainboard/supermicro/h8qgi/platform_oem.h
+++ b/src/mainboard/supermicro/h8qgi/platform_oem.h
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 08b0eb2be1..08b0eb2be1 100755..100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
index 90b53357ad..90b53357ad 100755..100644
--- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 70b3a0470d..70b3a0470d 100755..100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index d80e2d5935..12fc4469ab 100644
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -58,7 +58,7 @@ void main(unsigned long bist)
 	SystemPreInit();
 
 	cs5536_early_setup();
-	
+
 	/* cs5536_disable_internal_uart	 disable them. Set them up now... */
 	cs5536_setup_onchipuart(1);
 
diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h
index e6f9d81b83..e6f9d81b83 100755..100644
--- a/src/northbridge/amd/agesa/family10/amdfam10.h
+++ b/src/northbridge/amd/agesa/family10/amdfam10.h
diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c
index f6ae8be8b9..f6ae8be8b9 100755..100644
--- a/src/northbridge/amd/agesa/family10/bootblock.c
+++ b/src/northbridge/amd/agesa/family10/bootblock.c
diff --git a/src/northbridge/amd/agesa/family10/chip.h b/src/northbridge/amd/agesa/family10/chip.h
index c0ac56e5a9..c0ac56e5a9 100755..100644
--- a/src/northbridge/amd/agesa/family10/chip.h
+++ b/src/northbridge/amd/agesa/family10/chip.h
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index b3e4c63d00..b3e4c63d00 100755..100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
diff --git a/src/northbridge/amd/agesa/family10/northbridge.h b/src/northbridge/amd/agesa/family10/northbridge.h
index 0530ee7495..0530ee7495 100755..100644
--- a/src/northbridge/amd/agesa/family10/northbridge.h
+++ b/src/northbridge/amd/agesa/family10/northbridge.h
diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h
index 5b24f2d63a..5b24f2d63a 100755..100644
--- a/src/northbridge/amd/agesa/family10/reset_test.h
+++ b/src/northbridge/amd/agesa/family10/reset_test.h
diff --git a/src/northbridge/amd/agesa/family10/root_complex/chip.h b/src/northbridge/amd/agesa/family10/root_complex/chip.h
index 15a2e1ae69..15a2e1ae69 100755..100644
--- a/src/northbridge/amd/agesa/family10/root_complex/chip.h
+++ b/src/northbridge/amd/agesa/family10/root_complex/chip.h
diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c
index 6ec4da9c9f..6ec4da9c9f 100755..100644
--- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c
+++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c
diff --git a/src/northbridge/amd/agesa/family12/bootblock.c b/src/northbridge/amd/agesa/family12/bootblock.c
index eead31d26b..f6ae8be8b9 100755..100644
--- a/src/northbridge/amd/agesa/family12/bootblock.c
+++ b/src/northbridge/amd/agesa/family12/bootblock.c
@@ -20,7 +20,7 @@
  * ***************************************************************************
  *
  */
- 
+
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
diff --git a/src/northbridge/amd/agesa/family12/chip.h b/src/northbridge/amd/agesa/family12/chip.h
index 462610d6ea..462610d6ea 100755..100644
--- a/src/northbridge/amd/agesa/family12/chip.h
+++ b/src/northbridge/amd/agesa/family12/chip.h
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index 55109b57be..2c039d2b4e 100755..100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -311,7 +311,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
         }
 
 #if 0
-        // We need to double check if there is speical set on base reg and limit reg 
+        // We need to double check if there is speical set on base reg and limit reg
             // are not continous instead of hole, it will find out it's hole_startk
         if(mem_hole.node_id==-1) {
             resource_t limitk_pri = 0;
@@ -332,7 +332,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
             }
         }
 #endif
-        
+
         return mem_hole;
 }
 #endif
@@ -471,7 +471,7 @@ static void set_resources(device_t dev)
     struct resource *res;
 
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - set_resources - Start.\n");
- 
+
     /* Find the nodeid */
     nodeid = amdfam12_nodeid(dev);
 
@@ -782,7 +782,7 @@ static void domain_enable_resources(device_t dev)
   /* Must be called after PCI enumeration and resource allocation */
 //  printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - agesawrapper_amdinitmid - Start.\n");
   printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - Start.\n");
-//  val = agesawrapper_amdinitmid (); 
+//  val = agesawrapper_amdinitmid ();
 //  if(val) {
 //    printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
 //  }
@@ -819,7 +819,7 @@ static void cpu_bus_set_resources(device_t dev)
     pci_dev_set_resources(dev);
     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_set_resources - End.\n");
 }
- 
+
 static void cpu_bus_init(device_t dev)
 {
     u32 val;
@@ -830,20 +830,20 @@ static void cpu_bus_init(device_t dev)
 #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - Start.\n");
-    sb_After_Pci_Init (); 
+    sb_After_Pci_Init ();
     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - End.\n");
 #endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
 
 #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - Start.\n");
-    sb_Mid_Post_Init (); 
+    sb_Mid_Post_Init ();
     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - End.\n");
 #endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
 
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - agesawrapper_amdinitmid - Start.\n");
-    val = agesawrapper_amdinitmid (); 
+    val = agesawrapper_amdinitmid ();
     if(val) {
         printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
     }
diff --git a/src/northbridge/amd/agesa/family12/northbridge.h b/src/northbridge/amd/agesa/family12/northbridge.h
index 8de80ff501..8de80ff501 100755..100644
--- a/src/northbridge/amd/agesa/family12/northbridge.h
+++ b/src/northbridge/amd/agesa/family12/northbridge.h
diff --git a/src/northbridge/amd/agesa/family12/root_complex/chip.h b/src/northbridge/amd/agesa/family12/root_complex/chip.h
index 91599252fc..91599252fc 100755..100644
--- a/src/northbridge/amd/agesa/family12/root_complex/chip.h
+++ b/src/northbridge/amd/agesa/family12/root_complex/chip.h
diff --git a/src/northbridge/amd/agesa/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c
index eead31d26b..f6ae8be8b9 100644
--- a/src/northbridge/amd/agesa/family14/bootblock.c
+++ b/src/northbridge/amd/agesa/family14/bootblock.c
@@ -20,7 +20,7 @@
  * ***************************************************************************
  *
  */
- 
+
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index b410bb96d6..99518065de 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -958,7 +958,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
 //           byte 1 - fid_max
 //           byte 2 - nb_cof_vid_update
 //           byte 3 - apic id
-   
+
 #define LAPIC_MSG_REG 0x380
 #define F10_APSTATE_STARTED 0x13  // start of AP execution
 #define F10_APSTATE_STOPPED 0x14  // allow AP to stop
diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h
index 566e1fbbb0..ccee1fdff0 100644
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -292,8 +292,8 @@
 #define CUR_PSTATE_MSR 0xc0010063
 #define TSC_FREQ_SEL_SHIFT 24
 
-#define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT) 
- 
+#define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT)
+
 #define  WAIT_PSTATE_TIMEOUT 80000000  /* 0.1 s , unit : 1.25 ns */
 
 #endif
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 8b50eed790..a262686f87 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -673,7 +673,7 @@ static void setup_uniprocessor(void)
 }
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
-static int optimize_connection_group(const u8 *opt_conn, int num) 
+static int optimize_connection_group(const u8 *opt_conn, int num)
 {
 	int needs_reset = 0;
 	int i;
@@ -1709,7 +1709,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
 		}
 #endif
 
-		
+
 #if CONFIG_K8_REV_F_SUPPORT == 0
 		/* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
 		if (!is_cpu_pre_b3())
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 4533818ef8..7ba2b90406 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -48,7 +48,7 @@ static void mcf3_read_resources(device_t dev)
 	}
 
 	iommu = 1;
-	if( get_option(&iommu, "iommu") < 0 ) 
+	if( get_option(&iommu, "iommu") < 0 )
 	{
 		iommu = CONFIG_IOMMU;
 	}
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index a62036621f..319293b7ed 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1815,7 +1815,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 #endif
 #endif
 	];
-	
+
 	if (bios_cycle_time > min_cycle_time) {
 		min_cycle_time = bios_cycle_time;
 	}
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index d2bef3868e..ae1537f24c 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -140,7 +140,7 @@
 #define BU_CFG2		0xC001102A
 
 /*
- * Processor package types 
+ * Processor package types
  */
 #define AMD_PKGTYPE_FrX_1207 0
 #define AMD_PKGTYPE_AM3_2r2 1
diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
index f7c6b5af25..37b138a6da 100644
--- a/src/northbridge/intel/i82830/smihandler.c
+++ b/src/northbridge/intel/i82830/smihandler.c
@@ -196,7 +196,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id)
 			}
 
 			mbi_header = (mbi_header_t *)&mbi[i];
-			len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16); 
+			len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
 
 			if (obj_header->objnum == count) {
 #ifdef DEBUG_SMI_I82830
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 85ba1be4f0..23c3cb14d1 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -831,12 +831,12 @@ static void spd_set_dram_throttle_control(void)
 	 */
 	dtc_reg |= (3 << 28);
 
-	/* Read Counter Based Power Throttle Control (RCTC): 
+	/* Read Counter Based Power Throttle Control (RCTC):
 	 *   0 = 85%
 	 */
 	dtc_reg |= (0 << 24);
 
-	/* Write Counter Based Power Throttle Control (WCTC): 
+	/* Write Counter Based Power Throttle Control (WCTC):
 	 *   0 = 85%
 	 */
 	dtc_reg |= (0 << 20);
@@ -879,7 +879,7 @@ static void spd_update(u8 reg, u32 new_value)
 	u32 value2 = pci_read_config32(NORTHBRIDGE_MMC, reg);
 	PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2);
 #endif
-}	
+}
 
 /* if ram still doesn't work do this function */
 static void spd_set_undocumented_registers(void)
@@ -967,7 +967,7 @@ static void sdram_set_spd_registers(void)
 	if (dimm_mask == 0) {
 		print_debug("No usable memory for this controller\n");
 	} else {
-		PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);	
+		PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);
 
 		spd_set_row_attributes(dimm_mask);
 		spd_set_dram_controller_mode(dimm_mask);
diff --git a/src/northbridge/via/cx700/northbridge.h b/src/northbridge/via/cx700/northbridge.h
index 4ae9ce5937..c651bfe5f2 100644
--- a/src/northbridge/via/cx700/northbridge.h
+++ b/src/northbridge/via/cx700/northbridge.h
@@ -21,6 +21,6 @@
 #define NORTHBRIDGE_VIA_CX700_H
 
 extern unsigned int cx700_scan_root_bus(device_t root, unsigned int max);
-extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
+extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,
 		u32 esi, u32 edi) __attribute__((regparm(0)));
 #endif				/* NORTHBRIDGE_VIA_CX700_H */
diff --git a/src/northbridge/via/vt8623/northbridge.h b/src/northbridge/via/vt8623/northbridge.h
index 9c0828741c..176a590490 100644
--- a/src/northbridge/via/vt8623/northbridge.h
+++ b/src/northbridge/via/vt8623/northbridge.h
@@ -2,7 +2,7 @@
 #define NORTHBRIDGE_VIA_VT8623_H
 
 unsigned int vt8623_scan_root_bus(device_t root, unsigned int max);
-extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
+extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,
 		u32 esi, u32 edi) __attribute__((regparm(0)));
 
 #endif /* NORTHBRIDGE_VIA_VT8623_H */
diff --git a/src/northbridge/via/vx800/northbridge.h b/src/northbridge/via/vx800/northbridge.h
index 05f75d2649..4b51bb7c11 100644
--- a/src/northbridge/via/vx800/northbridge.h
+++ b/src/northbridge/via/vx800/northbridge.h
@@ -21,7 +21,7 @@
 #define NORTHBRIDGE_VIA_VX800_H
 
 extern unsigned int vx800_scan_root_bus(device_t root, unsigned int max);
-extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
+extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,
 		u32 esi, u32 edi) __attribute__((regparm(0)));
 
 #endif				/* NORTHBRIDGE_VIA_VX800_H */
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index d7317a23a2..db5343dff0 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -20,7 +20,7 @@
  * ***************************************************************************
  *
  */
- 
+
 #ifndef  _AMD_SBPLATFORM_H_
 #define  _AMD_SBPLATFORM_H_
 
@@ -112,7 +112,7 @@ typedef union _PCI_ADDR {
  */
 #define SB_CIMx_PARAMETER  0x02
 
-// Generic 
+// Generic
 #define cimSpreadSpectrumDefault        TRUE
 #define cimSpreadSpectrumTypeDefault	0x00      // Normal
 #define cimHpetTimerDefault             TRUE
@@ -121,7 +121,7 @@ typedef union _PCI_ADDR {
 #define cimSpiFastReadEnableDefault     0x01      // Enable
 #define cimSpiFastReadSpeedDefault      0x01      // 33 MHz
 #define cimSioHwmPortEnableDefault      FALSE
-// GPP/AB Controller 
+// GPP/AB Controller
 #define cimNbSbGen2Default              TRUE
 #define cimAlinkPhyPllPowerDownDefault  TRUE
 #define cimResetCpuOnSyncFloodDefault   TRUE
@@ -129,13 +129,13 @@ typedef union _PCI_ADDR {
 #define cimGppMemWrImproveDefault       TRUE
 #define cimGppPortAspmDefault           FALSE
 #define cimGppLaneReversalDefault       FALSE
-#define cimGppPhyPllPowerDownDefault    TRUE 
+#define cimGppPhyPllPowerDownDefault    TRUE
 // USB Controller
 #define cimUsbPhyPowerDownDefault       FALSE
 // GEC Controller
 #define cimSBGecDebugBusDefault         FALSE
 #define cimSBGecPwrDefault              0x03
-// Sata Controller 
+// Sata Controller
 #define cimSataSetMaxGen2Default        0x00
 #define cimSATARefClkSelDefault         0x10
 #define cimSATARefDivSelDefault         0x80
@@ -143,11 +143,11 @@ typedef union _PCI_ADDR {
 #define cimSataPortMultCapDefault       TRUE
 #define cimSataPscCapDefault            0x00      // Enable
 #define cimSataSscCapDefault            0x00      // Enable
-#define cimSataFisBasedSwitchingDefault FALSE 
+#define cimSataFisBasedSwitchingDefault FALSE
 #define cimSataCccSupportDefault        FALSE
 #define cimSataClkAutoOffDefault        FALSE
 #define cimNativepciesupportDefault     FALSE
-// Fusion Related 
+// Fusion Related
 #define cimAcDcMsgDefault               FALSE
 #define cimTimerTickTrackDefault        FALSE
 #define cimClockInterruptTagDefault     FALSE
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 593bd6bfc7..0a339b02f7 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -39,8 +39,8 @@ static void enable_rom(void)
 	pci_io_write_config32(dev, 0x44, dword);
 
 	/* SB800 LPC Bridge 0:20:3:48h.
-	 * BIT0: Port Enable for SuperIO 0x2E-0x2F 
-	 * BIT1: Port Enable for SuperIO 0x4E-0x4F 
+	 * BIT0: Port Enable for SuperIO 0x2E-0x2F
+	 * BIT1: Port Enable for SuperIO 0x4E-0x4F
 	 * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
 	 * BIT6: Port Enable for RTC IO 0x70-0x73
 	 * BIT21: Port Enable for Port 0x80
diff --git a/src/southbridge/amd/cimx/sb900/Amd.h b/src/southbridge/amd/cimx/sb900/Amd.h
index cfb983c2cf..cfb983c2cf 100755..100644
--- a/src/southbridge/amd/cimx/sb900/Amd.h
+++ b/src/southbridge/amd/cimx/sb900/Amd.h
diff --git a/src/southbridge/amd/cimx/sb900/AmdSbLib.h b/src/southbridge/amd/cimx/sb900/AmdSbLib.h
index a86f24b6fb..a86f24b6fb 100755..100644
--- a/src/southbridge/amd/cimx/sb900/AmdSbLib.h
+++ b/src/southbridge/amd/cimx/sb900/AmdSbLib.h
diff --git a/src/southbridge/amd/cimx/sb900/SbEarly.h b/src/southbridge/amd/cimx/sb900/SbEarly.h
index 5e2b05cfdc..5e2b05cfdc 100755..100644
--- a/src/southbridge/amd/cimx/sb900/SbEarly.h
+++ b/src/southbridge/amd/cimx/sb900/SbEarly.h
diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h
index 3fb45dea64..3fb45dea64 100755..100644
--- a/src/southbridge/amd/cimx/sb900/SbPlatform.h
+++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index e04cec0e04..e84743bc20 100755..100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -73,8 +73,8 @@ static void sb900_enable_rom(void)
   pci_io_write_config32(dev, 0x44, dword);
 
   /* SB900 LPC Bridge 0:20:3:48h.
-   * BIT0: Port Enable for SuperIO 0x2E-0x2F 
-   * BIT1: Port Enable for SuperIO 0x4E-0x4F 
+   * BIT0: Port Enable for SuperIO 0x2E-0x2F
+   * BIT1: Port Enable for SuperIO 0x4E-0x4F
    * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
    * BIT6: Port Enable for RTC IO 0x70-0x73
    * BIT21: Port Enable for Port 0x80
@@ -86,7 +86,7 @@ static void sb900_enable_rom(void)
   /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
   /* Set the 4MB enable bits */
   word = pci_io_read_config16(dev, 0x6c);
-  word = 0xFFC0; 
+  word = 0xFFC0;
   pci_io_write_config16(dev, 0x6c, word);
 }
 
diff --git a/src/southbridge/amd/cimx/sb900/cbtypes.h b/src/southbridge/amd/cimx/sb900/cbtypes.h
index 4c97a33ed6..4c97a33ed6 100755..100644
--- a/src/southbridge/amd/cimx/sb900/cbtypes.h
+++ b/src/southbridge/amd/cimx/sb900/cbtypes.h
diff --git a/src/southbridge/amd/cimx/sb900/chip.h b/src/southbridge/amd/cimx/sb900/chip.h
index 96afc42736..96afc42736 100755..100644
--- a/src/southbridge/amd/cimx/sb900/chip.h
+++ b/src/southbridge/amd/cimx/sb900/chip.h
diff --git a/src/southbridge/amd/cimx/sb900/chip_name.c b/src/southbridge/amd/cimx/sb900/chip_name.c
index dd875dcfd6..dd875dcfd6 100755..100644
--- a/src/southbridge/amd/cimx/sb900/chip_name.c
+++ b/src/southbridge/amd/cimx/sb900/chip_name.c
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index bd4fd4fa22..1176ca598c 100755..100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -142,7 +142,7 @@ void sb_Late_Post(void)
 	//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
 	// VerifyImage() will fail, LocateImage() take minitues to find the image.
 	sbLatePost(&sb_early_cfg);
-	
+
 	//Set ACPI SCI IRQ to 0x9.
 	data = CONFIG_ACPI_SCI_IRQ;
 	outb(0x10, 0xC00);
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 71c65e31c6..71c65e31c6 100755..100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c
index 48bfe36556..48bfe36556 100755..100644
--- a/src/southbridge/amd/cimx/sb900/lpc.c
+++ b/src/southbridge/amd/cimx/sb900/lpc.c
diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h
index f4d1493fba..f4d1493fba 100755..100644
--- a/src/southbridge/amd/cimx/sb900/lpc.h
+++ b/src/southbridge/amd/cimx/sb900/lpc.h
diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c
index 1fbf5ac6c7..1fbf5ac6c7 100755..100644
--- a/src/southbridge/amd/cimx/sb900/smbus.c
+++ b/src/southbridge/amd/cimx/sb900/smbus.c
diff --git a/src/southbridge/amd/cimx/sb900/smbus.h b/src/southbridge/amd/cimx/sb900/smbus.h
index e6ade1ed48..e6ade1ed48 100755..100644
--- a/src/southbridge/amd/cimx/sb900/smbus.h
+++ b/src/southbridge/amd/cimx/sb900/smbus.h
diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c
index dba28e789a..5d816e59f4 100644
--- a/src/southbridge/amd/rs690/ht.c
+++ b/src/southbridge/amd/rs690/ht.c
@@ -28,25 +28,25 @@
 static void ht_dev_set_resources(device_t dev)
 {
 #if CONFIG_EXT_CONF_SUPPORT == 1
-	unsigned reg;		
+	unsigned reg;
 	device_t k8_f1;
 	resource_t rbase, rend;
 	u32 base, limit;
 	struct resource *resource;
-	
+
 	printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
-	
+
 	resource = probe_resource(dev, 0x1C);
 	if (resource) {
-		set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); // make bar3 visible	
+		set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); // make bar3 visible
 		set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 1 << 30);	/* Enables writes to the BAR3 register. */
-		set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); // program bus range: 255 busses 
+		set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); // program bus range: 255 busses
 		pci_write_config32(dev, 0x1C, resource->base);
 		/* Enable MMCONFIG decoding. */
 		set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28);	/* PCIEMiscInit */
 		set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 0 << 30);	/* Disable writes to the BAR3 register. */
 		set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3
-		
+
 		// setup resource nonposted in k8 mmio
 		/* Get the base address */
 		rbase = resource->base;
@@ -74,9 +74,9 @@ static void ht_dev_set_resources(device_t dev)
 			limit &= 0x00000048;
 			limit |= ((rend >> 8) & 0xffffff00);
 			limit |= (sblk << 4);
-			limit |= (1 << 7); 
+			limit |= (1 << 7);
 			printk(BIOS_INFO, "%s <- index %x base %04x limit %04x\n", dev_path(k8_f1), reg, base, limit);
-			pci_write_config32(k8_f1, reg+4, limit); 
+			pci_write_config32(k8_f1, reg+4, limit);
 			pci_write_config32(k8_f1, reg, base);
 		}
 	}
@@ -88,13 +88,13 @@ static void ht_dev_read_resources(device_t dev)
 {
 #if CONFIG_EXT_CONF_SUPPORT == 1
 	struct resource *res;
-	
-	printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);	
-	set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3	
+
+	printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
+	set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3
 #endif
 
 	pci_dev_read_resources(dev);
-	
+
 #if CONFIG_EXT_CONF_SUPPORT == 1
 	/* Add an MMCONFIG resource. */
 	res = new_resource(dev, 0x1C);
@@ -104,9 +104,9 @@ static void ht_dev_read_resources(device_t dev)
 	res->gran = log2(res->size);
 	res->limit = 0xffffffffffffffffULL;	/* 64bit */
 	res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED;
-	
+
 	compact_resources(dev);
-#endif	
+#endif
 }
 
 /* for UMA internal graphics */
diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c
index 4bd870bbf2..40a72627e0 100644
--- a/src/southbridge/amd/rs780/cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
@@ -381,7 +381,7 @@ u32 extractbits(u32 source, int lsb, int msb)
 int cpuidFamily(void)
 {
 	u32 baseFamily, extendedFamily, fms;
-	
+
 	fms = cpuid_eax (1);
 	baseFamily = extractbits (fms, 8, 11);
 	extendedFamily = extractbits (fms, 20, 27);
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 3c06d441ce..65a5e2bd2f 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -511,7 +511,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 			vgainfo.ucUMAChannelNumber = 2;
 		}
 	}
-      
+
 	// processor type
 	if (is_family0Fh())
 		vgainfo.ulCPUCapInfo = 3;
@@ -539,9 +539,9 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 
 	/* HT width. */
 	value = pci_read_config8(nb_dev, 0xcb);
-	vgainfo.usMinDownStreamHTLinkWidth = 
-	vgainfo.usMaxDownStreamHTLinkWidth = 
-	vgainfo.usMinUpStreamHTLinkWidth = 
+	vgainfo.usMinDownStreamHTLinkWidth =
+	vgainfo.usMaxDownStreamHTLinkWidth =
+	vgainfo.usMinUpStreamHTLinkWidth =
 	vgainfo.usMaxUpStreamHTLinkWidth =
 	vgainfo.usMinHTLinkWidth =
 	vgainfo.usMaxHTLinkWidth = ht_width_lookup [extractbits(value, 0, 2)];
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index cf6d2dfb1a..717aeab2c6 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -223,7 +223,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 #if (CONFIG_GFXUMA == 1)
 	extern uint64_t uma_memory_size;
 	// bits 7-9: aperture size
-	// 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g 
+	// 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g
 	if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;
 	if (uma_memory_size == 0x04000000) romstrap2 |= 2 << 7;
 	if (uma_memory_size == 0x08000000) romstrap2 |= 0 << 7;
diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c
index 7eda2e854c..121e3d7cbf 100644
--- a/src/southbridge/amd/sb600/sata.c
+++ b/src/southbridge/amd/sb600/sata.c
@@ -123,8 +123,8 @@ static void sata_init(struct device *dev)
 		// no cmos option
 		i = CONFIG_SATA_MODE;
 	}
-	printk(BIOS_INFO, "%s: setting sata mode = %s\n", __func__, (i == SATA_MODE_IDE)?"ide":"ahci" );	
-	
+	printk(BIOS_INFO, "%s: setting sata mode = %s\n", __func__, (i == SATA_MODE_IDE)?"ide":"ahci" );
+
 	dword = pci_read_config32(dev, 0x8);
 	dword &= 0xff0000ff;
 	if (i == SATA_MODE_IDE)
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 1f46da2228..1f46da2228 100755..100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c
index 4652ca2539..5f415fb9f2 100644
--- a/src/southbridge/amd/sb700/ide.c
+++ b/src/southbridge/amd/sb700/ide.c
@@ -51,8 +51,8 @@ static void ide_init(struct device *dev)
 
 	/* set ide as primary, if you want to boot from IDE, you'd better set it
 	 * in $vendor/$mainboard/devicetree.cb */
-	 
-	
+
+
 	if (conf->boot_switch_sata_ide == 1) {
 		struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 		byte = pci_read_config8(sm_dev, 0xAD);
diff --git a/src/southbridge/amd/sb700/pmio.c b/src/southbridge/amd/sb700/pmio.c
index baded54ba6..baded54ba6 100755..100644
--- a/src/southbridge/amd/sb700/pmio.c
+++ b/src/southbridge/amd/sb700/pmio.c
diff --git a/src/southbridge/amd/sb700/pmio.h b/src/southbridge/amd/sb700/pmio.h
index 207fdc24ab..207fdc24ab 100755..100644
--- a/src/southbridge/amd/sb700/pmio.h
+++ b/src/southbridge/amd/sb700/pmio.h
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
index 27ca32eb5e..27ca32eb5e 100755..100644
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index 58b72ad538..58b72ad538 100755..100644
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 165c72d52b..165c72d52b 100755..100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 05065b6dbe..05065b6dbe 100755..100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
diff --git a/src/southbridge/amd/sb700/smbus.c b/src/southbridge/amd/sb700/smbus.c
index 6edc3de80c..6edc3de80c 100755..100644
--- a/src/southbridge/amd/sb700/smbus.c
+++ b/src/southbridge/amd/sb700/smbus.c
diff --git a/src/southbridge/amd/sb700/smbus.h b/src/southbridge/amd/sb700/smbus.h
index 9ddfc35303..9ddfc35303 100755..100644
--- a/src/southbridge/amd/sb700/smbus.h
+++ b/src/southbridge/amd/sb700/smbus.h
diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c
index 793240187f..793240187f 100755..100644
--- a/src/southbridge/amd/sb700/usb.c
+++ b/src/southbridge/amd/sb700/usb.c
diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h
index 6692b86d1f..6692b86d1f 100755..100644
--- a/src/southbridge/amd/sr5650/cmn.h
+++ b/src/southbridge/amd/sr5650/cmn.h
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index 50f836e77c..50f836e77c 100755..100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index eebe711cdb..eebe711cdb 100755..100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index 14b919de72..14b919de72 100755..100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h
index 1b5112b7c2..1b5112b7c2 100755..100644
--- a/src/southbridge/amd/sr5650/sr5650.h
+++ b/src/southbridge/amd/sr5650/sr5650.h
diff --git a/src/southbridge/ti/pcixx12/chip.h b/src/southbridge/ti/pcixx12/chip.h
index 68612499c5..42dc79cd1a 100644
--- a/src/southbridge/ti/pcixx12/chip.h
+++ b/src/southbridge/ti/pcixx12/chip.h
@@ -24,7 +24,7 @@ extern struct chip_operations southbridge_ti_pcixx12_ops;
 
 struct southbridge_ti_pcixx12_config {
 	int dummy;
-	
+
 };
 
 #endif /* _SOUTHBRIDGE_TI_PCIXX12 */
diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c
index 701b93d5f1..1b21b32166 100644
--- a/src/southbridge/via/k8t890/bridge.c
+++ b/src/southbridge/via/k8t890/bridge.c
@@ -27,7 +27,7 @@ static void bridge_enable(struct device *dev)
 {
 	u8 tmp;
 	print_debug("B188 device dump\n");
-	
+
 	/* VIA recommends this, sorry no known info. */
 
 	writeback(dev, 0x40, 0x91);
diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c
index a2a5fe9edc..42676b1770 100644
--- a/src/southbridge/via/k8t890/ctrl.c
+++ b/src/southbridge/via/k8t890/ctrl.c
@@ -34,7 +34,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb)
 	u8 regm, regm3;
 
 	device_t devfun3;
-	
+
 	devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
 					   PCI_DEVICE_ID_VIA_K8T800_DRAM, 0);
 
@@ -45,7 +45,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb)
 	if (!devfun3)
 		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
 					   PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
-		
+
 	if (!devfun3)
 		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
 					   PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
@@ -53,12 +53,12 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb)
 	if (!devfun3)
 		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
 					   PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
-	
+
 	if(!devfun3)
 		die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n");
 
 	pci_write_config8(dev, 0x70, 0xc2);
-	
+
 	/* PCI Control */
 	pci_write_config8(dev, 0x72, 0xee);
 	pci_write_config8(dev, 0x73, 0x01);
@@ -157,7 +157,7 @@ static void vt8237r_vlink_init(struct device *dev)
 	pci_write_config8(dev, 0x48, 0xa3);
 }
 
-static void ctrl_init(struct device *dev) 
+static void ctrl_init(struct device *dev)
 {
 
 	print_debug("K8x8xx: Initializing V-Link to VT8237R sb: ");
diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c
index dd65b508ca..9b43a5e57f 100644
--- a/src/southbridge/via/k8t890/dram.c
+++ b/src/southbridge/via/k8t890/dram.c
@@ -65,7 +65,7 @@ static void dram_enable(struct device *dev)
 
 	/* The Address Next to the Last Valid DRAM Address */
 	pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg);
-	
+
 	print_debug(" VIA_X_3 device dump:\n");
 	dump_south(dev);
 
diff --git a/src/southbridge/via/k8t890/error.c b/src/southbridge/via/k8t890/error.c
index a5f86bf4e9..f2cab10db0 100644
--- a/src/southbridge/via/k8t890/error.c
+++ b/src/southbridge/via/k8t890/error.c
@@ -36,7 +36,7 @@ static void error_enable(struct device *dev)
 
 	print_debug("Done\n");
 	/* TODO: enable AGP errors reporting on K8M890 */
-	
+
 	print_debug(" VIA_X_1 device dump:\n");
 	dump_south(dev);
 }
diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h
index 7f30f3b7a3..a0fb57ab3c 100644
--- a/src/southbridge/via/k8t890/k8x8xx.h
+++ b/src/southbridge/via/k8t890/k8x8xx.h
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2011  Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software: you can redistribute it and/or modify
@@ -12,7 +12,7 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 3e2f215751..e59951702f 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -297,7 +297,7 @@ static void vt8237r_init(struct device *dev)
 	 */
 	pci_write_config8(dev, 0x48, 0x0c);
 #else
-	
+
   #if CONFIG_SOUTHBRIDGE_VIA_K8T800
 	/* It seems that when we pair with the K8T800, we need to disable
 	 * the A2 mask
@@ -310,7 +310,7 @@ static void vt8237r_init(struct device *dev)
 	 */
 	pci_write_config8(dev, 0x48, 0x8c);
   #endif
-	
+
 #endif
 
 	southbridge_init_common(dev);
@@ -327,7 +327,7 @@ static void vt8237r_init(struct device *dev)
 
 	printk(BIOS_SPEW, "Leaving %s.\n", __func__);
 	printk(BIOS_SPEW, "And taking a dump:\n");
-	dump_south(dev);	
+	dump_south(dev);
 }
 
 static void vt8237a_init(struct device *dev)
diff --git a/src/superio/fintek/f71805f/chip.h b/src/superio/fintek/f71805f/chip.h
index 6e9c6c9241..60eb684a32 100644
--- a/src/superio/fintek/f71805f/chip.h
+++ b/src/superio/fintek/f71805f/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_fintek_f71805f_ops;
 
 struct superio_fintek_f71805f_config {
-	
+
 };
 
 #endif
diff --git a/src/superio/fintek/f71859/chip.h b/src/superio/fintek/f71859/chip.h
index 84008623e1..157ed26ab1 100755..100644
--- a/src/superio/fintek/f71859/chip.h
+++ b/src/superio/fintek/f71859/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_fintek_f71859_ops;
 
 struct superio_fintek_f71859_config {
-	
+
 };
 
 #endif
diff --git a/src/superio/fintek/f71859/early_serial.c b/src/superio/fintek/f71859/early_serial.c
index 14d22a6310..14d22a6310 100755..100644
--- a/src/superio/fintek/f71859/early_serial.c
+++ b/src/superio/fintek/f71859/early_serial.c
diff --git a/src/superio/fintek/f71859/f71859.h b/src/superio/fintek/f71859/f71859.h
index b9aed6e0ff..b9aed6e0ff 100755..100644
--- a/src/superio/fintek/f71859/f71859.h
+++ b/src/superio/fintek/f71859/f71859.h
diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c
index 809140b5a1..809140b5a1 100755..100644
--- a/src/superio/fintek/f71859/superio.c
+++ b/src/superio/fintek/f71859/superio.c
diff --git a/src/superio/fintek/f71863fg/chip.h b/src/superio/fintek/f71863fg/chip.h
index ce9fd480b2..ade7498e35 100644
--- a/src/superio/fintek/f71863fg/chip.h
+++ b/src/superio/fintek/f71863fg/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_fintek_f71863fg_ops;
 
 struct superio_fintek_f71863fg_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/fintek/f71872/chip.h b/src/superio/fintek/f71872/chip.h
index 58ee4217ca..bd41dd679d 100644
--- a/src/superio/fintek/f71872/chip.h
+++ b/src/superio/fintek/f71872/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_fintek_f71872_ops;
 
 struct superio_fintek_f71872_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/fintek/f71889/chip.h b/src/superio/fintek/f71889/chip.h
index c7752164cb..65ae8700ab 100644
--- a/src/superio/fintek/f71889/chip.h
+++ b/src/superio/fintek/f71889/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_fintek_f71889_ops;
 
 struct superio_fintek_f71889_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/fintek/f81865f/chip.h b/src/superio/fintek/f81865f/chip.h
index 6ff30012ca..711e2d0a58 100644
--- a/src/superio/fintek/f81865f/chip.h
+++ b/src/superio/fintek/f81865f/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_fintek_f81865f_ops;
 
 struct superio_fintek_f81865f_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/ite/it8661f/chip.h b/src/superio/ite/it8661f/chip.h
index 744316e0e4..64b2cf873f 100644
--- a/src/superio/ite/it8661f/chip.h
+++ b/src/superio/ite/it8661f/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_ite_it8661f_ops;
 
 struct superio_ite_it8661f_config {
-	
+
 };
 
 #endif
diff --git a/src/superio/ite/it8671f/chip.h b/src/superio/ite/it8671f/chip.h
index 3dd2d81a5b..7fa7e26f57 100644
--- a/src/superio/ite/it8671f/chip.h
+++ b/src/superio/ite/it8671f/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_ite_it8671f_ops;
 
 struct superio_ite_it8671f_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/ite/it8673f/chip.h b/src/superio/ite/it8673f/chip.h
index 431098e433..126180a19f 100644
--- a/src/superio/ite/it8673f/chip.h
+++ b/src/superio/ite/it8673f/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_ite_it8673f_ops;
 
 struct superio_ite_it8673f_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/ite/it8705f/chip.h b/src/superio/ite/it8705f/chip.h
index be4a8d7b6d..df620a8906 100644
--- a/src/superio/ite/it8705f/chip.h
+++ b/src/superio/ite/it8705f/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_ite_it8705f_ops;
 
 struct superio_ite_it8705f_config {
-	
+
 };
 
 #endif
diff --git a/src/superio/ite/it8712f/chip.h b/src/superio/ite/it8712f/chip.h
index 76401099df..18630066db 100644
--- a/src/superio/ite/it8712f/chip.h
+++ b/src/superio/ite/it8712f/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_ite_it8712f_ops;
 
 struct superio_ite_it8712f_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/ite/it8716f/chip.h b/src/superio/ite/it8716f/chip.h
index 0c2f387a3e..16b69ce261 100644
--- a/src/superio/ite/it8716f/chip.h
+++ b/src/superio/ite/it8716f/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_ite_it8716f_ops;
 
 struct superio_ite_it8716f_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/ite/it8718f/chip.h b/src/superio/ite/it8718f/chip.h
index 78044aa1d7..43f7152fbb 100644
--- a/src/superio/ite/it8718f/chip.h
+++ b/src/superio/ite/it8718f/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_ite_it8718f_ops;
 
 struct superio_ite_it8718f_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/nsc/pc8374/chip.h b/src/superio/nsc/pc8374/chip.h
index ec0a57a617..4ae78f8ac0 100644
--- a/src/superio/nsc/pc8374/chip.h
+++ b/src/superio/nsc/pc8374/chip.h
@@ -29,7 +29,7 @@ extern struct chip_operations superio_nsc_pc8374_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc8374_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/nsc/pc87309/chip.h b/src/superio/nsc/pc87309/chip.h
index 8a612245bd..b9f5a7a9f9 100644
--- a/src/superio/nsc/pc87309/chip.h
+++ b/src/superio/nsc/pc87309/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_nsc_pc87309_ops;
 
 struct superio_nsc_pc87309_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/nsc/pc87351/chip.h b/src/superio/nsc/pc87351/chip.h
index cb835c7963..46b56afb71 100644
--- a/src/superio/nsc/pc87351/chip.h
+++ b/src/superio/nsc/pc87351/chip.h
@@ -29,7 +29,7 @@ extern struct chip_operations superio_nsc_pc87351_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc87351_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/nsc/pc87360/chip.h b/src/superio/nsc/pc87360/chip.h
index 712176dd8a..0cc6a89ee7 100644
--- a/src/superio/nsc/pc87360/chip.h
+++ b/src/superio/nsc/pc87360/chip.h
@@ -29,7 +29,7 @@ extern struct chip_operations superio_nsc_pc87360_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc87360_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/nsc/pc87366/chip.h b/src/superio/nsc/pc87366/chip.h
index 75ce691ac0..6f656d4a65 100644
--- a/src/superio/nsc/pc87366/chip.h
+++ b/src/superio/nsc/pc87366/chip.h
@@ -28,7 +28,7 @@ extern struct chip_operations superio_nsc_pc87366_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc87366_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/nsc/pc87382/chip.h b/src/superio/nsc/pc87382/chip.h
index 18d570ad1e..8cc049f52f 100644
--- a/src/superio/nsc/pc87382/chip.h
+++ b/src/superio/nsc/pc87382/chip.h
@@ -25,7 +25,7 @@
 extern struct chip_operations superio_nsc_pc87382_ops;
 
 struct superio_nsc_pc87382_config {
-	
+
 };
 
 #endif
diff --git a/src/superio/nsc/pc87384/chip.h b/src/superio/nsc/pc87384/chip.h
index d006478962..ef202fc68b 100644
--- a/src/superio/nsc/pc87384/chip.h
+++ b/src/superio/nsc/pc87384/chip.h
@@ -25,7 +25,7 @@
 extern struct chip_operations superio_nsc_pc87384_ops;
 
 struct superio_nsc_pc87384_config {
-	
+
 };
 
 #endif
diff --git a/src/superio/nsc/pc87392/chip.h b/src/superio/nsc/pc87392/chip.h
index 1241cb2f44..8b5fc52bfe 100644
--- a/src/superio/nsc/pc87392/chip.h
+++ b/src/superio/nsc/pc87392/chip.h
@@ -26,7 +26,7 @@ extern struct chip_operations superio_nsc_pc87392_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc87392_config {
-	
+
 };
 
 #endif
diff --git a/src/superio/nsc/pc87417/chip.h b/src/superio/nsc/pc87417/chip.h
index a66bb40a97..ec3c381c92 100644
--- a/src/superio/nsc/pc87417/chip.h
+++ b/src/superio/nsc/pc87417/chip.h
@@ -29,7 +29,7 @@ extern struct chip_operations superio_nsc_pc87417_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc87417_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/nsc/pc87427/chip.h b/src/superio/nsc/pc87427/chip.h
index d044fe09ff..610dbdf8f7 100644
--- a/src/superio/nsc/pc87427/chip.h
+++ b/src/superio/nsc/pc87427/chip.h
@@ -28,7 +28,7 @@ extern struct chip_operations superio_nsc_pc87427_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc87427_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/nsc/pc97307/chip.h b/src/superio/nsc/pc97307/chip.h
index 838d36b9e2..cc43323f79 100644
--- a/src/superio/nsc/pc97307/chip.h
+++ b/src/superio/nsc/pc97307/chip.h
@@ -34,7 +34,7 @@ extern struct chip_operations superio_nsc_pc97307_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc97307_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 #endif
diff --git a/src/superio/nsc/pc97317/chip.h b/src/superio/nsc/pc97317/chip.h
index 6c415f6aee..4eb0c19cd9 100644
--- a/src/superio/nsc/pc97317/chip.h
+++ b/src/superio/nsc/pc97317/chip.h
@@ -34,7 +34,7 @@ extern struct chip_operations superio_nsc_pc97317_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc97317_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/nuvoton/wpcm450/chip.h b/src/superio/nuvoton/wpcm450/chip.h
index 2afc2de597..c921120501 100644
--- a/src/superio/nuvoton/wpcm450/chip.h
+++ b/src/superio/nuvoton/wpcm450/chip.h
@@ -28,7 +28,7 @@ extern struct chip_operations superio_nuvoton_wpcm450_ops;
 #include <uart8250.h>
 
 struct superio_nuvoton_wpcm450_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/nuvoton/wpcm450/early_init.c b/src/superio/nuvoton/wpcm450/early_init.c
index 94bef02ef7..94bef02ef7 100755..100644
--- a/src/superio/nuvoton/wpcm450/early_init.c
+++ b/src/superio/nuvoton/wpcm450/early_init.c
diff --git a/src/superio/nuvoton/wpcm450/wpcm450.h b/src/superio/nuvoton/wpcm450/wpcm450.h
index 46f3cc5fe6..46f3cc5fe6 100755..100644
--- a/src/superio/nuvoton/wpcm450/wpcm450.h
+++ b/src/superio/nuvoton/wpcm450/wpcm450.h
diff --git a/src/superio/smsc/fdc37m60x/chip.h b/src/superio/smsc/fdc37m60x/chip.h
index 2a1186fe0e..450ef75fbe 100644
--- a/src/superio/smsc/fdc37m60x/chip.h
+++ b/src/superio/smsc/fdc37m60x/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_smsc_fdc37m60x_ops;
 
 struct superio_smsc_fdc37m60x_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/smsc/fdc37n972/chip.h b/src/superio/smsc/fdc37n972/chip.h
index abaf765153..858cf532c1 100644
--- a/src/superio/smsc/fdc37n972/chip.h
+++ b/src/superio/smsc/fdc37n972/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_smsc_fdc37n972_ops;
 
 struct superio_smsc_fdc37n972_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/smsc/kbc1100/chip.h b/src/superio/smsc/kbc1100/chip.h
index 020224f650..40aff0bf7d 100644
--- a/src/superio/smsc/kbc1100/chip.h
+++ b/src/superio/smsc/kbc1100/chip.h
@@ -27,7 +27,7 @@ struct chip_operations;
 extern struct chip_operations superio_smsc_kbc1100_ops;
 
 struct superio_smsc_kbc1100_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/smsc/kbc1100/kbc1100_early_init.c b/src/superio/smsc/kbc1100/kbc1100_early_init.c
index 4247a96318..84aa4e0510 100644
--- a/src/superio/smsc/kbc1100/kbc1100_early_init.c
+++ b/src/superio/smsc/kbc1100/kbc1100_early_init.c
@@ -40,11 +40,11 @@ static inline void kbc1100_early_init(unsigned port)
   dev = PNP_DEV (port, KBC1100_KBC);
 
   pnp_enter_conf_state(dev);
-  
+
   /* Serial IRQ enabled */
   outb(0x25, port);
   outb(0x04, port + 1);
-  
+
   /* Enable SMSC UART 0 */
   dev = PNP_DEV (port, SMSCSUPERIO_SP1);
   pnp_set_logical_device(dev);
@@ -70,6 +70,6 @@ static inline void kbc1100_early_init(unsigned port)
   pnp_exit_conf_state(dev);
 
   /* disable the 1s timer */
-  outb(0xE7, 0x64);  
+  outb(0xE7, 0x64);
 }
 
diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c
index bd330bac4a..c4fde95960 100644
--- a/src/superio/smsc/kbc1100/superio.c
+++ b/src/superio/smsc/kbc1100/superio.c
@@ -97,14 +97,14 @@ static void kbc1100_init(device_t dev)
   struct superio_smsc_kbc1100_config *conf = dev->chip_info;
   struct resource *res0, *res1;
 
-  
-   
+
+
   if (!dev->enabled) {
     return;
   }
 
   switch(dev->path.pnp.device) {
-  
+
   case KBC1100_KBC:
     res0 = find_resource(dev, PNP_IDX_IO0);
     res1 = find_resource(dev, PNP_IDX_IO1);
diff --git a/src/superio/smsc/lpc47b272/chip.h b/src/superio/smsc/lpc47b272/chip.h
index 031cd20f55..754d63d967 100644
--- a/src/superio/smsc/lpc47b272/chip.h
+++ b/src/superio/smsc/lpc47b272/chip.h
@@ -28,7 +28,7 @@ extern struct chip_operations superio_smsc_lpc47b272_ops;
 #include <uart8250.h>
 
 struct superio_smsc_lpc47b272_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/smsc/lpc47b397/chip.h b/src/superio/smsc/lpc47b397/chip.h
index 3f3c719bf4..48fc6e475d 100644
--- a/src/superio/smsc/lpc47b397/chip.h
+++ b/src/superio/smsc/lpc47b397/chip.h
@@ -30,7 +30,7 @@ extern struct chip_operations superio_smsc_lpc47b397_ops;
 #include <uart8250.h>
 
 struct superio_smsc_lpc47b397_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/smsc/lpc47m10x/chip.h b/src/superio/smsc/lpc47m10x/chip.h
index 79b72dae43..6d6ee97603 100644
--- a/src/superio/smsc/lpc47m10x/chip.h
+++ b/src/superio/smsc/lpc47m10x/chip.h
@@ -32,7 +32,7 @@ extern struct chip_operations superio_smsc_lpc47m10x_ops;
 #include <uart8250.h>
 
 struct superio_smsc_lpc47m10x_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/smsc/lpc47m15x/chip.h b/src/superio/smsc/lpc47m15x/chip.h
index 27031f21b2..57aba06dd8 100644
--- a/src/superio/smsc/lpc47m15x/chip.h
+++ b/src/superio/smsc/lpc47m15x/chip.h
@@ -27,7 +27,7 @@ extern struct chip_operations superio_smsc_lpc47m15x_ops;
 #include <uart8250.h>
 
 struct superio_smsc_lpc47m15x_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/smsc/lpc47n217/chip.h b/src/superio/smsc/lpc47n217/chip.h
index c29031a85c..89a778c22c 100644
--- a/src/superio/smsc/lpc47n217/chip.h
+++ b/src/superio/smsc/lpc47n217/chip.h
@@ -27,7 +27,7 @@ extern struct chip_operations superio_smsc_lpc47n217_ops;
 #include <uart8250.h>
 
 struct superio_smsc_lpc47n217_config {
-	
+
 };
 
 #endif
diff --git a/src/superio/smsc/lpc47n227/chip.h b/src/superio/smsc/lpc47n227/chip.h
index fa0269971c..8b3a2c9dfc 100644
--- a/src/superio/smsc/lpc47n227/chip.h
+++ b/src/superio/smsc/lpc47n227/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_smsc_lpc47n227_ops;
 
 struct superio_smsc_lpc47n227_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c
index c7ffd69624..a241eb6d36 100644
--- a/src/superio/smsc/lpc47n227/superio.c
+++ b/src/superio/smsc/lpc47n227/superio.c
@@ -85,7 +85,7 @@ static void enable_dev(device_t dev)
  *
  * NOTE: Cannot use pnp_set_resources() here because it assumes chip
  * support for logical devices, which the LPC47N227 doesn't have.
- * 
+ *
  * @param dev Pointer to structure describing a Super I/O device.
  */
 void lpc47n227_pnp_set_resources(device_t dev)
diff --git a/src/superio/smsc/sio10n268/chip.h b/src/superio/smsc/sio10n268/chip.h
index 32703bb394..cd6e87bede 100644
--- a/src/superio/smsc/sio10n268/chip.h
+++ b/src/superio/smsc/sio10n268/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_smsc_sio10n268_ops;
 
 struct superio_smsc_sio10n268_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/smsc/smscsuperio/chip.h b/src/superio/smsc/smscsuperio/chip.h
index ffe4b21ce3..86f93be58d 100644
--- a/src/superio/smsc/smscsuperio/chip.h
+++ b/src/superio/smsc/smscsuperio/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_smsc_smscsuperio_ops;
 
 struct superio_smsc_smscsuperio_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/via/vt1211/chip.h b/src/superio/via/vt1211/chip.h
index 2154996a44..3fcd6ae1b1 100644
--- a/src/superio/via/vt1211/chip.h
+++ b/src/superio/via/vt1211/chip.h
@@ -26,7 +26,7 @@
 extern struct chip_operations superio_via_vt1211_ops;
 
 struct superio_via_vt1211_config {
-	
+
 };
 
 #endif
diff --git a/src/superio/winbond/w83627dhg/chip.h b/src/superio/winbond/w83627dhg/chip.h
index 51c56e892b..b516aacad0 100644
--- a/src/superio/winbond/w83627dhg/chip.h
+++ b/src/superio/winbond/w83627dhg/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_winbond_w83627dhg_ops;
 
 struct superio_winbond_w83627dhg_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/winbond/w83627ehg/chip.h b/src/superio/winbond/w83627ehg/chip.h
index f3fe8ce9e2..a16135dc0e 100644
--- a/src/superio/winbond/w83627ehg/chip.h
+++ b/src/superio/winbond/w83627ehg/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_winbond_w83627ehg_ops;
 
 struct superio_winbond_w83627ehg_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/winbond/w83627hf/chip.h b/src/superio/winbond/w83627hf/chip.h
index 14793ddbfe..64d9920464 100644
--- a/src/superio/winbond/w83627hf/chip.h
+++ b/src/superio/winbond/w83627hf/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_winbond_w83627hf_ops;
 
 struct superio_winbond_w83627hf_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/winbond/w83627thg/chip.h b/src/superio/winbond/w83627thg/chip.h
index 8da6954b90..ce06485665 100644
--- a/src/superio/winbond/w83627thg/chip.h
+++ b/src/superio/winbond/w83627thg/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_winbond_w83627thg_ops;
 
 struct superio_winbond_w83627thg_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/winbond/w83627uhg/chip.h b/src/superio/winbond/w83627uhg/chip.h
index ffabfa5fed..2802382ab9 100644
--- a/src/superio/winbond/w83627uhg/chip.h
+++ b/src/superio/winbond/w83627uhg/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_winbond_w83627uhg_ops;
 
 struct superio_winbond_w83627uhg_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h
index dd54a525ca..1a1cbcc038 100644
--- a/src/superio/winbond/w83697hf/chip.h
+++ b/src/superio/winbond/w83697hf/chip.h
@@ -26,7 +26,7 @@
 extern struct chip_operations superio_winbond_w83697hf_ops;
 
 struct superio_winbond_w83697hf_config {
-	
+
 };
 
 #endif
diff --git a/src/superio/winbond/w83977f/chip.h b/src/superio/winbond/w83977f/chip.h
index 1c126971de..aacb00918c 100644
--- a/src/superio/winbond/w83977f/chip.h
+++ b/src/superio/winbond/w83977f/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_winbond_w83977f_ops;
 
 struct superio_winbond_w83977f_config {
-	
+
 	struct pc_keyboard keyboard;
 };
 
diff --git a/src/superio/winbond/w83977tf/chip.h b/src/superio/winbond/w83977tf/chip.h
index cc24fc0e62..80c4afd856 100644
--- a/src/superio/winbond/w83977tf/chip.h
+++ b/src/superio/winbond/w83977tf/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_winbond_w83977tf_ops;
 
 struct superio_winbond_w83977tf_config {
-	
+
 	struct pc_keyboard keyboard;
 };
author	Stefan Reinauer <reinauer@chromium.org>	2011-10-31 12:56:45 -0700
committer	Patrick Georgi <patrick@georgi-clan.de>	2011-11-01 19:07:45 +0100
commit	5ff7c13e858a31addf1558731a12cf6c753b576d (patch)
tree	82ed6cf7b45f3a86c2c43ab87383355ed6012d6c /src
parent	784544b934d67dc85ccfcf33e04ff148045836ad (diff)