diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-01-01 19:21:28 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-10 10:17:37 +0000 |
| commit | 5c74911f7107c5fc3739252f407dc3553d0278ce (patch) | |
| tree | c508d9fba259912a0ad16e592c94dcf611d68b93 /src | |
| parent | d2f3afcc17df44589bd1f8b09e5c3a33edf64982 (diff) | |
mb/asus/p5qc/devicetree.cb: Drop zero values
They default to zero already. Moreover, the comment about AHCI mode no
longer applies, as it was made the default mode.
Change-Id: Ife99a79df0289c6db87510ed917438bf47b7f6ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb | 5 | ||||
| -rw-r--r-- | src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb | 5 | ||||
| -rw-r--r-- | src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb | 5 |
3 files changed, 3 insertions, 12 deletions
diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index e2340b9f03..f697bff010 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -37,10 +37,7 @@ chip northbridge/intel/x4x # Northbridge chip southbridge/intel/i82801jx # Southbridge register "gpe0_en" = "0x40" - # Set AHCI mode. - register "sata_port_map" = "0x3f" - register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" + register "sata_port_map" = "0x3f" # Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0x31" diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb index ebaaecaad2..94ef717e60 100644 --- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb @@ -37,10 +37,7 @@ chip northbridge/intel/x4x # Northbridge chip southbridge/intel/i82801jx # Southbridge register "gpe0_en" = "0x40" - # Set AHCI mode. - register "sata_port_map" = "0x3f" - register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" + register "sata_port_map" = "0x3f" # Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0x31" diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb index 4e27b467d9..91e45b4f29 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb @@ -37,10 +37,7 @@ chip northbridge/intel/x4x # Northbridge chip southbridge/intel/i82801jx # Southbridge register "gpe0_en" = "0x40" - # Set AHCI mode. - register "sata_port_map" = "0x3f" - register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" + register "sata_port_map" = "0x3f" # Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0x31" |