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authorDuncan Laurie <dlaurie@google.com>2020-03-17 18:49:39 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-31 10:42:20 +0000
commit516967c681a1cadfb053d8f4c098826eca743131 (patch)
tree058b591a832e7c11331f16725961036043b0520e /src
parentb40e780f8bf8f23337cf5125afdd4c3e04ec5d8c (diff)
mb/emulation/qemu-q35: Enable option for TPM
This enables the mainboard to use a TPM if it is selected in the configuration. By default this does nothing, but it allows the TPM to be enabled and used with the CONFIG_USER_TPM2 Kconfig option. Using a TPM with QEMU requires either a physical TPM backend or the swtpm package with a socket: -chardev socket,id=swtpm,path=/tmp/swtpm/socket -tpmdev emulator,id=tpm0,chardev=swtpm -device tpm-tis,tpmdev=tpm0 Change-Id: I0d79a5a0f590c57998ababb660b52d9e3ed2d484 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/emulation/qemu-q35/Kconfig1
-rw-r--r--src/mainboard/emulation/qemu-q35/devicetree.cb6
2 files changed, 6 insertions, 1 deletions
diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig
index 71841fb591..ee6406049c 100644
--- a/src/mainboard/emulation/qemu-q35/Kconfig
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_16384 if VBOOT
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_FORCE_NATIVE_VGA_INIT
+ select MAINBOARD_HAS_LPC_TPM
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/mainboard/emulation/qemu-q35/devicetree.cb b/src/mainboard/emulation/qemu-q35/devicetree.cb
index c032606e67..ff0589fa60 100644
--- a/src/mainboard/emulation/qemu-q35/devicetree.cb
+++ b/src/mainboard/emulation/qemu-q35/devicetree.cb
@@ -8,7 +8,11 @@ chip mainboard/emulation/qemu-q35
device pci 0.0 mandatory end # northbridge (q35)
chip southbridge/intel/i82801ix
# present unconditionally
- device pci 1f.0 mandatory end # LPC
+ device pci 1f.0 mandatory
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end # LPC
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMBus