mb/intel/mtlrvp: Enable ChromeOS build for mtlrvp

This patch enables building ChromeOS for mtlrvp.
Patch includes,
1. Add cros_gpios for mtlrvp
2. Add chrome OS configuration in Kconfig
3. Add Chromeos.c

BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train (CB: 69886)

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ia428941bd8269714c3edca6c7b0c2a3fbf08bd75
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70724
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 65 insertions, 0 deletions

diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index f5255675f3..a571bb50dc 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -3,6 +3,7 @@ config BOARD_INTEL_MTLRVP_COMMON
 	select BOARD_ROMSIZE_KB_32768
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select MAINBOARD_HAS_CHROMEOS
 	select SOC_INTEL_METEORLAKE
 
 config BOARD_INTEL_MTLRVP_P
@@ -13,6 +14,14 @@ config BOARD_INTEL_MTLRVP_P_EXT_EC
 
 if BOARD_INTEL_MTLRVP_COMMON
 
+config CHROMEOS
+	select GBB_FLAG_FORCE_DEV_BOOT_ALTFW
+	select GBB_FLAG_FORCE_DEV_SWITCH_ON
+	select GBB_FLAG_FORCE_DEV_BOOT_USB
+	select GBB_FLAG_FORCE_MANUAL_RECOVERY
+	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+	select HAS_RECOVERY_MRC_CACHE
+
 config MAINBOARD_DIR
 	default "intel/mtlrvp"
 
@@ -20,6 +29,11 @@ config BASEBOARD_DIR
 	string
 	default "mtlrvp_p" if BOARD_INTEL_MTLRVP_P || BOARD_INTEL_MTLRVP_P_EXT_EC
 
+config GBB_HWID
+	string
+	depends on CHROMEOS
+	default "MTLRVP"
+
 config MAINBOARD_PART_NUMBER
 	string
 	default "mtlrvp"
diff --git a/src/mainboard/intel/mtlrvp/Makefile.inc b/src/mainboard/intel/mtlrvp/Makefile.inc
index 56ec7bd7f5..0bd89131ba 100644
--- a/src/mainboard/intel/mtlrvp/Makefile.inc
+++ b/src/mainboard/intel/mtlrvp/Makefile.inc
@@ -1,5 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 
+all-$(CONFIG_CHROMEOS) += chromeos.c
+
 ramstage-y += ec.c
 ramstage-y += mainboard.c
 
diff --git a/src/mainboard/intel/mtlrvp/chromeos.c b/src/mainboard/intel/mtlrvp/chromeos.c
new file mode 100644
index 0000000000..bb6df26c45
--- /dev/null
+++ b/src/mainboard/intel/mtlrvp/chromeos.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <bootmode.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <types.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+		{-1, ACTIVE_HIGH, 0, "EC in RW"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES)
+int get_lid_switch(void)
+{
+	/* Lid always open */
+	return 1;
+}
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}
+#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */
+
+int get_write_protect_state(void)
+{
+	/* No write protect */
+	return 0;
+}
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc
new file mode 100644
index 0000000000..eb2c9bc021
--- /dev/null
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c
new file mode 100644
index 0000000000..3e41a46a7d
--- /dev/null
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+};
+DECLARE_CROS_GPIOS(cros_gpios);