diff options
| author | Tristan Shieh <tristan.shieh@mediatek.com> | 2019-08-16 15:35:50 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-08-21 09:28:29 +0000 |
| commit | 4b5eefa675cc1d1853d9f35bbecafbf0e6e9886d (patch) | |
| tree | 5ebfd1f99b3bb2916c555b799847194886e477cd /src | |
| parent | 526d840b13386d76ddbd5130f82940130e621dc4 (diff) | |
mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE region
Enlarge PRERAM_CBFS_CACHE region from (16K - 4) to (48K - 4) bytes to
decompress and load more data from CBFS in romstage.
BUG=b:134351649
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: Idc23a67c886718e910ca3c50468e5793f19c8d66
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34896
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/memlayout.ld | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index d8d5f6660a..73c880afbf 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -32,11 +32,11 @@ SECTIONS VBOOT2_TPM_LOG(0x00103000, 2K) PRERAM_CBMEM_CONSOLE(0x00103800, 14K) WATCHDOG_TOMBSTONE(0x00107000, 4) - PRERAM_CBFS_CACHE(0x00107004, 16K - 4) - TIMESTAMP(0x0010B000, 4K) - STACK(0x0010C000, 16K) - TTB(0x00110000, 28K) - DMA_COHERENT(0x00117000, 4K) + PRERAM_CBFS_CACHE(0x00107004, 48K - 4) + TIMESTAMP(0x00113000, 4K) + STACK(0x00114000, 16K) + TTB(0x00118000, 28K) + DMA_COHERENT(0x0011f000, 4K) SRAM_END(0x00120000) SRAM_L2C_START(0x00200000) |