nb/intel/sandybridge: add and use defines for PCI_DEV(0,0,0) registers

This patch didn't change the resulting binary for an X230 when using
TIMELESS_BUILD=1

Change-Id: Ibeb10c3e0c04dec76892a86fa39e60543b2ee2f5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

4 files changed, 47 insertions, 41 deletions

diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c
index a8f8603f02..50fc7555f6 100644
--- a/src/northbridge/intel/sandybridge/finalize.c
+++ b/src/northbridge/intel/sandybridge/finalize.c
@@ -21,18 +21,18 @@
 
 void intel_sandybridge_finalize_smm(void)
 {
-	pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0);	/* GGC */
-	pci_or_config16(PCI_DEV_SNB, 0x58, 1 << 2);	/* PAVP Lock */
-	pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0);	/* DPR */
+	pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0);
+	pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2);
+	pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0);
 	pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10);	/* ME */
-	pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0);	/* REMAPBASE */
-	pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0);	/* REMAPLIMIT */
-	pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0);	/* TOM */
-	pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0);	/* TOUUD */
-	pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0);	/* BDSM */
-	pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0);	/* BGSM */
-	pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0);	/* TSEGMB */
-	pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0);	/* TOLUD */
+	pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0);
+	pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0);
+	pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0);
+	pci_or_config32(PCI_DEV_SNB, TOUUD, 1 << 0);
+	pci_or_config32(PCI_DEV_SNB, BDSM, 1 << 0);
+	pci_or_config32(PCI_DEV_SNB, BGSM, 1 << 0);
+	pci_or_config32(PCI_DEV_SNB, TSEGMB, 1 << 0);
+	pci_or_config32(PCI_DEV_SNB, TOLUD, 1 << 0);
 
 	MCHBAR32_OR(0x5500, 1 << 0);	/* PAVP */
 	MCHBAR32_OR(0x5f00, 1 << 31);	/* SA PM */
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index 99888fa2ae..6ebd7e0bb6 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -27,7 +27,7 @@
 static uintptr_t smm_region_start(void)
 {
 	/* Base of TSEG is top of usable DRAM */
-	uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
+	uintptr_t tom = pci_read_config32(PCI_DEV(0, 0, 0), TSEGMB);
 	return tom;
 }
 
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 44e5d3a8ff..2a521575d8 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -521,68 +521,68 @@ void dram_memorymap(ramctr_timing * ctrl, int me_uma_size)
 	printk(BIOS_DEBUG, "Update PCI-E configuration space:\n");
 
 	// TOM (top of memory)
-	reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xa0);
+	reg = pci_read_config32(PCI_DEV(0, 0, 0), TOM);
 	val = tom & 0xfff;
 	reg = (reg & ~0xfff00000) | (val << 20);
-	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa0, reg);
-	pci_write_config32(PCI_DEV(0, 0, 0), 0xa0, reg);
+	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM, reg);
+	pci_write_config32(PCI_DEV(0, 0, 0), TOM, reg);
 
-	reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xa4);
+	reg = pci_read_config32(PCI_DEV(0, 0, 0), TOM + 4);
 	val = tom & 0xfffff000;
 	reg = (reg & ~0x000fffff) | (val >> 12);
-	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa4, reg);
-	pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, reg);
+	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg);
+	pci_write_config32(PCI_DEV(0, 0, 0), TOM + 4, reg);
 
 	// TOLUD (top of low used dram)
-	reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xbc);
+	reg = pci_read_config32(PCI_DEV(0, 0, 0), TOLUD);
 	val = toludbase & 0xfff;
 	reg = (reg & ~0xfff00000) | (val << 20);
-	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xbc, reg);
-	pci_write_config32(PCI_DEV(0, 0, 0), 0xbc, reg);
+	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg);
+	pci_write_config32(PCI_DEV(0, 0, 0), TOLUD, reg);
 
 	// TOUUD LSB (top of upper usable dram)
-	reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xa8);
+	reg = pci_read_config32(PCI_DEV(0, 0, 0), TOUUD);
 	val = touudbase & 0xfff;
 	reg = (reg & ~0xfff00000) | (val << 20);
-	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa8, reg);
-	pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, reg);
+	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg);
+	pci_write_config32(PCI_DEV(0, 0, 0), TOUUD, reg);
 
 	// TOUUD MSB
-	reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xac);
+	reg = pci_read_config32(PCI_DEV(0, 0, 0), TOUUD + 4);
 	val = touudbase & 0xfffff000;
 	reg = (reg & ~0x000fffff) | (val >> 12);
-	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xac, reg);
-	pci_write_config32(PCI_DEV(0, 0, 0), 0xac, reg);
+	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD + 4, reg);
+	pci_write_config32(PCI_DEV(0, 0, 0), TOUUD + 4, reg);
 
 	if (reclaim) {
 		// REMAP BASE
-		pci_write_config32(PCI_DEV(0, 0, 0), 0x90, remapbase << 20);
-		pci_write_config32(PCI_DEV(0, 0, 0), 0x94, remapbase >> 12);
+		pci_write_config32(PCI_DEV(0, 0, 0), REMAPBASE, remapbase << 20);
+		pci_write_config32(PCI_DEV(0, 0, 0), REMAPBASE + 4, remapbase >> 12);
 
 		// REMAP LIMIT
-		pci_write_config32(PCI_DEV(0, 0, 0), 0x98, remaplimit << 20);
-		pci_write_config32(PCI_DEV(0, 0, 0), 0x9c, remaplimit >> 12);
+		pci_write_config32(PCI_DEV(0, 0, 0), REMAPLIMIT, remaplimit << 20);
+		pci_write_config32(PCI_DEV(0, 0, 0), REMAPLIMIT + 4, remaplimit >> 12);
 	}
 	// TSEG
-	reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xb8);
+	reg = pci_read_config32(PCI_DEV(0, 0, 0), TSEGMB);
 	val = tsegbase & 0xfff;
 	reg = (reg & ~0xfff00000) | (val << 20);
-	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb8, reg);
-	pci_write_config32(PCI_DEV(0, 0, 0), 0xb8, reg);
+	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg);
+	pci_write_config32(PCI_DEV(0, 0, 0), TSEGMB, reg);
 
 	// GFX stolen memory
-	reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xb0);
+	reg = pci_read_config32(PCI_DEV(0, 0, 0), BDSM);
 	val = gfxstolenbase & 0xfff;
 	reg = (reg & ~0xfff00000) | (val << 20);
-	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb0, reg);
-	pci_write_config32(PCI_DEV(0, 0, 0), 0xb0, reg);
+	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg);
+	pci_write_config32(PCI_DEV(0, 0, 0), BDSM, reg);
 
 	// GTT stolen memory
-	reg = pci_read_config32(PCI_DEV(0, 0, 0), 0xb4);
+	reg = pci_read_config32(PCI_DEV(0, 0, 0), BGSM);
 	val = gttbase & 0xfff;
 	reg = (reg & ~0xfff00000) | (val << 20);
-	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb4, reg);
-	pci_write_config32(PCI_DEV(0, 0, 0), 0xb4, reg);
+	printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BGSM, reg);
+	pci_write_config32(PCI_DEV(0, 0, 0), BGSM, reg);
 
 	if (me_uma_size) {
 		reg = pci_read_config32(PCI_DEV(0, 0, 0), 0x7c);
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index dff943dd92..54fa66f2f6 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -79,6 +79,9 @@ enum platform_type {
 #define  DEVEN_PEG12	(1 << 1)
 #define  DEVEN_HOST	(1 << 0)
 
+#define PAVPC		0x58	/* Protected Audio Video Path Control */
+#define DPR		0x5c	/* DMA Protected Range */
+
 #define PAM0		0x80
 #define PAM1		0x81
 #define PAM2		0x82
@@ -90,10 +93,13 @@ enum platform_type {
 #define LAC		0x87	/* Legacy Access Control */
 #define SMRAM		0x88	/* System Management RAM Control */
 
+#define REMAPBASE	0x90
+#define REMAPLIMIT	0x98
 #define TOM		0xa0
 #define TOUUD		0xa8	/* Top of Upper Usable DRAM */
+#define BDSM		0xb0	/* Base Data of Stolen Memory */
 #define BGSM		0xb4	/* Base GTT Stolen Memory */
-#define TSEG		0xb8	/* TSEG base */
+#define TSEGMB		0xb8	/* TSEG Memory Base */
 #define TOLUD		0xbc	/* Top of Low Used Memory */
 
 #define CAPID0_A	0xe4	/* Capabilities Register A */