diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-09-17 18:48:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-20 13:35:29 +0000 |
| commit | 43d2527203121be776d3e532c09ca46c2a8afaf9 (patch) | |
| tree | 36f892e7a7d25d04c08e4690b1018db085d88e9e /src | |
| parent | 8370f6b79c06bcea1a04f53e9028d0aa447e3583 (diff) | |
soc/intel/skylake: lockdown: lock global reset
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only
one (apollolake) is actually calling the code. Add the missing call.
Also fix the register offset in a comment in reset code.
Tested successfully on X11SSM-F by reading ETR3.
Change-Id: If190c3c66889ede105d958b423b38ebdcb698332
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36573
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/lockdown.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/reset.c | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 69459e7e03..66dae8c73c 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -16,6 +16,7 @@ #include <device/mmio.h> #include <intelblocks/cfg.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/pmclib.h> #include <intelpch/lockdown.h> #include <soc/pm.h> @@ -38,6 +39,9 @@ static void pmc_lockdown_config(void) pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); pmsyncreg |= PMSYNC_LOCK; write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); + + /* Make sure payload/OS can't trigger global reset */ + pmc_global_reset_disable_and_lock(); } void soc_lockdown_config(int chipset_lockdown) diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index ff1a959194..8f5bf30946 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -26,7 +26,7 @@ static void do_force_global_reset(void) /* * BIOS should ensure it does a global reset * to reset both host and Intel ME by setting - * PCH PMC [B0:D31:F2 register offset 0x1048 bit 20] + * PCH PMC [B0:D31:F2 register offset 0xAC bit 20] */ pmc_global_reset_enable(true); |