mb/system76/darp7: Add System76 Darter Pro 7

https://tech-docs.system76.com/models/darp7/README.html

Tested with TianoCore (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe SSD
- M.2 SATA SSD
- MicroSD card reader
- All USB ports
- USB-PD
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- HDMI output
- DP over USB-C output
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone/microphone jack
- S0ix suspend*
- Booting to Ubuntu Linux 21.04 and Windows 10
- Flashing with flashrom

Not working:

- S0ix when a device is attached to the TBT port

Not tested:

- Thunderbolt functionality

Change-Id: I80e5c5375f9d3881fc89a45a91ba68ed2e104a93
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52349
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

18 files changed, 867 insertions, 0 deletions

diff --git a/src/mainboard/system76/darp7/Kconfig b/src/mainboard/system76/darp7/Kconfig
new file mode 100644
index 0000000000..4af6768163
--- /dev/null
+++ b/src/mainboard/system76/darp7/Kconfig
@@ -0,0 +1,55 @@
+if BOARD_SYSTEM76_DARP7
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_PMC
+	select DRIVERS_INTEL_USB4_RETIMER
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
+	select SOC_INTEL_TIGERLAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+
+config MAINBOARD_DIR
+	default "system76/darp7"
+
+config MAINBOARD_PART_NUMBER
+	default "darp7"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Darter Pro"
+
+config MAINBOARD_VERSION
+	default "darp7"
+
+config CBFS_SIZE
+	default 0xA00000
+
+config CONSOLE_POST
+	default y
+
+config DIMM_SPD_SIZE
+	default 512
+
+config POST_DEVICE
+	default n
+
+config UART_FOR_CONSOLE
+	default 2
+
+endif
diff --git a/src/mainboard/system76/darp7/Kconfig.name b/src/mainboard/system76/darp7/Kconfig.name
new file mode 100644
index 0000000000..7994cd4fb0
--- /dev/null
+++ b/src/mainboard/system76/darp7/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_DARP7
+	bool "darp7"
diff --git a/src/mainboard/system76/darp7/Makefile.inc b/src/mainboard/system76/darp7/Makefile.inc
new file mode 100644
index 0000000000..af14dce4e5
--- /dev/null
+++ b/src/mainboard/system76/darp7/Makefile.inc
@@ -0,0 +1,8 @@
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += gpio_early.c
+
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/system76/darp7/acpi/mainboard.asl b/src/mainboard/system76/darp7/acpi/mainboard.asl
new file mode 100644
index 0000000000..4675bc94b8
--- /dev/null
+++ b/src/mainboard/system76/darp7/acpi/mainboard.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x6E
+#define EC_GPE_SWI 0x6B
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
diff --git a/src/mainboard/system76/darp7/acpi/sleep.asl b/src/mainboard/system76/darp7/acpi/sleep.asl
new file mode 100644
index 0000000000..83888f3e59
--- /dev/null
+++ b/src/mainboard/system76/darp7/acpi/sleep.asl
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/gpio.h>
+
+Method (PGPM, 1, Serialized)
+{
+	For (Local0 = 0, Local0 < 6, Local0++)
+	{
+		\_SB.PCI0.CGPM (Local0, Arg0)
+	}
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+	PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+	PGPM (0)
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.PEPD._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+	If (Arg0 == 1) {
+		/* S0ix Entry */
+		PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
+	} Else {
+		/* S0ix Exit */
+		PGPM (0)
+	}
+}
diff --git a/src/mainboard/system76/darp7/board_info.txt b/src/mainboard/system76/darp7/board_info.txt
new file mode 100644
index 0000000000..b28efd4444
--- /dev/null
+++ b/src/mainboard/system76/darp7/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: darp7
+Category: laptop
+Release year: 2021
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/system76/darp7/bootblock.c b/src/mainboard/system76/darp7/bootblock.c
new file mode 100644
index 0000000000..8d06adc9d7
--- /dev/null
+++ b/src/mainboard/system76/darp7/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <mainboard/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	mainboard_configure_early_gpios();
+}
diff --git a/src/mainboard/system76/darp7/cmos.default b/src/mainboard/system76/darp7/cmos.default
new file mode 100644
index 0000000000..d56495357c
--- /dev/null
+++ b/src/mainboard/system76/darp7/cmos.default
@@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Enable
diff --git a/src/mainboard/system76/darp7/cmos.layout b/src/mainboard/system76/darp7/cmos.layout
new file mode 100644
index 0000000000..ca7c7a4c5c
--- /dev/null
+++ b/src/mainboard/system76/darp7/cmos.layout
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	384	r	0	reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+409	2	e	7	power_on_after_fail
+412	4	e	6	debug_level
+984	16	h	0	check_sum
+
+enumerations
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
+checksums
+
+checksum 408 983 984
diff --git a/src/mainboard/system76/darp7/data.vbt b/src/mainboard/system76/darp7/data.vbt
new file mode 100644
index 0000000000..e3b164fd1d
--- /dev/null
+++ b/src/mainboard/system76/darp7/data.vbt
diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb
new file mode 100644
index 0000000000..c357ed1ac8
--- /dev/null
+++ b/src/mainboard/system76/darp7/devicetree.cb
@@ -0,0 +1,339 @@
+chip soc/intel/tigerlake
+	register "common_soc_config" = "{
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+# ACPI (soc/intel/tigerlake/acpi.c)
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+	# Enable s0ix, required for TGL-U
+	register "s0ix_enable" = "1"
+
+# CPU (soc/intel/tigerlake/cpu.c)
+	# Power limits
+	register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
+		.tdp_pl1_override = 28,
+		.tdp_pl2_override = 40,
+	}"
+	register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
+		.tdp_pl1_override = 28,
+		.tdp_pl2_override = 40,
+	}"
+
+# Finalize (soc/intel/tigerlake/finalize.c)
+	# PM Timer Disabled, saves power
+	register "PmTimerDisabled" = "1"
+
+# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
+	# Enable C6 DRAM
+	register "enable_c6dram" = "1"
+
+	# System Agent dynamic frequency support
+	register "SaGv" = "SaGv_Enabled"
+
+# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
+	# Acoustic settings
+	register "AcousticNoiseMitigation" = "1"
+	register "SlowSlewRate" = "SLEW_FAST_8"
+	register "FastPkgCRampDisable" = "1"
+
+	# FIVR configuration
+	#   Read EXT_RAIL_CONFIG to determine bitmaps
+	#     sudo devmem2 0xfe0011b8
+	#     0x0
+	#   Read EXT_V1P05_VR_CONFIG
+	#     sudo devmem2 0xfe0011c0
+	#     0x1a42000
+	#   Read EXT_VNN_VR_CONFIG0
+	#     sudo devmem2 0xfe0011c4
+	#     0x1a42000
+	# TODO: v1p05 voltage and vnn icc max?
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = 0,
+		.vnn_enable_bitmap = 0,
+		.v1p05_supported_voltage_bitmap = 0,
+		.vnn_supported_voltage_bitmap = 0,
+		.v1p05_icc_max_ma = 500,
+		.vnn_sx_voltage_mv = 1050,
+	}"
+
+	# Read LPM_EN, make sure to invert the bits
+	register "LpmStateDisableMask" = "
+		LPM_S0i2_1 |
+		LPM_S0i2_2 |
+		LPM_S0i3_1 |
+		LPM_S0i3_2 |
+		LPM_S0i3_3 |
+		LPM_S0i3_4
+	"
+
+	# Thermal
+	register "tcc_offset" = "12"
+
+	# Enable CNVi BT
+	register "CnviBtCore" = "true"
+
+# PM Util (soc/intel/tigerlake/pmutil.c)
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_A"
+	register "pmc_gpe0_dw1" = "PMC_GPP_R"
+	register "pmc_gpe0_dw2" = "PMC_GPD"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		subsystemid 0x1558 0x51a1 inherit
+
+		#From CPU EDS (575683)
+		device ref system_agent on end
+		device ref igpu on
+			# DDIA is eDP
+			register "DdiPortAConfig" = "1"
+			register "DdiPortAHpd" = "1"
+			register "DdiPortADdc" = "0"
+
+			# DDIB is HDMI
+			register "DdiPortBConfig" = "0"
+			register "DdiPortBHpd" = "1"
+			register "DdiPortBDdc" = "1"
+		end
+		device ref dptf on
+			register "Device4Enable" = "1"
+		end
+		device ref peg on
+			# PCIe PEG0 x4, Clock 0 (SSD1)
+			register "PcieClkSrcUsage[0]" = "0x40"
+			register "PcieClkSrcClkReq[0]" = "0"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST#
+				register "srcclk_pin" = "0" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref tbt_pcie_rp0 on end # J_TYPEC2
+		device ref north_xhci on # J_TYPEC2
+			register "UsbTcPortEn" = "1"
+			register "TcssXhciEn" = "1"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 3)"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref tbt_dma0 on # J_TYPEC2
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+
+		# From PCH EDS (576591)
+		device ref south_xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # UJ_USB1
+			register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH0
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1
+
+			# ACPI
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 UJ_USB1""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_TYPEC1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_USB3_1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Fingerprint""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 3)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_TYPEC1 CH0""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_USB3_1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_TYPEC1 CH1""
+						register "type" = "UPC_TYPE_A"
+						# TODO
+						#register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+		device ref shared_ram on end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref i2c1 on
+			# TODO: USB-PD?
+			register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+		end
+		device ref heci1 on
+			# TODO Disable ME and HECI
+			register "HeciEnabled" = "1"
+		end
+		device ref uart2 on
+			# Debug console
+			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
+		end
+		device ref sata on
+			# SATA1 (SSD0)
+			register "SataPortsEnable[1]" = "1"
+			register "SataPortsDevSlp[1]" = "1"
+			register "SataPortsEnableDitoConfig[1]" = "1"
+			register "SataSalpSupport" = "1"
+		end
+		device ref pcie_rp1 on
+			register "PcieRpLtrEnable[0]" = "1"
+		end
+		device ref pcie_rp6 on
+			# PCIe root port #6 x1, Clock 2 (CARD)
+			register "PcieRpEnable[5]" = "1"
+			register "PcieRpLtrEnable[5]" = "1"
+			register "PcieClkSrcUsage[2]" = "5"
+			register "PcieClkSrcClkReq[2]" = "2"
+		end
+		device ref pcie_rp7 on
+			# PCIe root port #7 x1, Clock 3 (GLAN)
+			register "PcieRpEnable[6]" = "1"
+			register "PcieRpLtrEnable[6]" = "1"
+			register "PcieClkSrcUsage[3]" = "6"
+			register "PcieClkSrcClkReq[3]" = "3"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # GPIO_LANRTD3
+				register "srcclk_pin" = "3" # GLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp8 on
+			# PCIe root port #8 x1, Clock 1 (WLAN)
+			register "PcieRpEnable[7]" = "1"
+			register "PcieRpLtrEnable[7]" = "1"
+			register "PcieClkSrcUsage[1]" = "7"
+			register "PcieClkSrcClkReq[1]" = "1"
+		end
+		device ref pcie_rp9 on
+			# PCIe root port #9 x4, Clock 4 (SSD0)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[4]" = "8"
+			register "PcieClkSrcClkReq[4]" = "4"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
+				register "srcclk_pin" = "4"
+				device generic 0 on end
+			end
+		end
+		device ref pch_espi on
+			register "gen1_dec" = "0x000c0081"
+			register "gen2_dec" = "0x00040069"
+			register "gen3_dec" = "0x00fc0E01"
+			register "gen4_dec" = "0x00fc0F01"
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref p2sb on end
+		device ref pmc hidden
+			# The pmc_mux chip driver is a placeholder for the
+			# PMC.MUX device in the ACPI hierarchy.
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						# J_TYPEC2
+						register "usb2_port_number" = "6"
+						register "usb3_port_number" = "1"
+						# SBU & HSL follow CC
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref hda on
+			register "PchHdaAudioLinkHdaEnable" = "1"
+		end
+		device ref smbus on
+			register "SmbusEnable" = "1"
+		end
+		device ref fast_spi on end
+	end
+end
diff --git a/src/mainboard/system76/darp7/dsdt.asl b/src/mainboard/system76/darp7/dsdt.asl
new file mode 100644
index 0000000000..fb40a5d67f
--- /dev/null
+++ b/src/mainboard/system76/darp7/dsdt.asl
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/tigerlake/acpi/southbridge.asl>
+		#include <soc/intel/tigerlake/acpi/tcss.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/system76/darp7/gpio.c b/src/mainboard/system76/darp7/gpio.c
new file mode 100644
index 0000000000..ad18ca6483
--- /dev/null
+++ b/src/mainboard/system76/darp7/gpio.c
@@ -0,0 +1,231 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW@
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_CFG_GPI(GPD2, NONE, PWROK), // LAN_WAKEUP#
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_NC(GPD6, NONE),
+	PAD_CFG_GPO(GPD7, 1, PWROK), // GPD7_REST
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPD9, 0, PWROK), // PCH_SLP_WLAN#_R / GPD9_RTD3
+	PAD_NC(GPD10, NONE),
+	PAD_CFG_GPI(GPD11, UP_20K, DEEP), // LAN_DISABLE#
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_AD0
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_AD1
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_AD2
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_AD3
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS#
+	PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_NC(GPP_A7, NONE),
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), // CNVI_RST#
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_NC(GPP_A10, NONE),
+	PAD_NC(GPP_A11, NONE),
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
+	PAD_NC(GPP_A14, NONE),
+	PAD_NC(GPP_A15, NONE),
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, NONE),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HDP
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_CFG_GPO(GPP_A23, 0, PLTRST), // GPP_A23_TBT_FORCE_PWR
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	PAD_CFG_GPI(GPP_B2, UP_20K, DEEP), // VRALERT#_PD
+	PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), // GPP_B3 - touchpad interrupt
+	PAD_NC(GPP_B4, NONE),
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_CFG_GPO(GPP_B8, 1, DEEP), // SB_BLON
+	PAD_NC(GPP_B9, NONE),
+	PAD_NC(GPP_B10, NONE),
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_GPO(GPP_B14, 0, DEEP), // PCH_SPKR
+	PAD_CFG_GPO(GPP_B15, 1, DEEP), // PCH_GPP_B15
+	_PAD_CFG_STRUCT(GPP_B16, 0x44000301, 0x0000), // SDD1_PWR_EN
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, NONE), // NO REBOOT strap
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP), // strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK / SMB_CLK_DDR
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA / SMB_DAT_DDR
+	PAD_NC(GPP_C2, NONE), // Intel ME Crypto TLS strap
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+	PAD_NC(GPP_C5, NONE), // boot config strap, bit 0
+	PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1), // TBT-PCH_I2C_SCL
+	PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1), // TBT-PCH_I2C_SDA
+	PAD_NC(GPP_C8, NONE),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	_PAD_CFG_STRUCT(GPP_C14, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SCL
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SDA
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL
+	//PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD
+	//PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD
+	PAD_CFG_GPO(GPP_C22, 1, PLTRST), // LAN_PLT_RST#
+	_PAD_CFG_STRUCT(GPP_C23, 0x40880100, 0x0000), // PCH_GPP_C23
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_CFG_GPI(GPP_D2, NONE, PLTRST), // GPP_D2_SDCARD_RST#
+	PAD_CFG_GPI(GPP_D3, NONE, PLTRST), // GPP_D3_WLAN_PLT_RST#
+	PAD_NC(GPP_D4, NONE),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD1_CLKREQ#
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // CARD_CLKREQ#
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GLAN_CLKREQ#
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE), // DPP3 I2C / TBT_LSX2 strap
+	PAD_CFG_GPI(GPP_D11, DN_20K, DEEP), // BOARD_ID
+	PAD_CFG_GPI(GPP_D12, DN_20K, DEEP), // DDP4 I2C / TBT_LSX3 strap
+	PAD_CFG_GPO(GPP_D13, 1, PLTRST), // GPP_D13_SSD1_PLT_RST#
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD_PWR_EN
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), // SATAGP0
+	PAD_CFG_GPO(GPP_E1, 0, PLTRST), // ROM_I2C_EN
+	_PAD_CFG_STRUCT(GPP_E2, 0x40880100, 0x0000), // SWI#
+	PAD_CFG_GPI(GPP_E3, DN_20K, DEEP), // SCI#
+	PAD_NC(GPP_E4, NONE), // DEVSLP0
+	PAD_NC(GPP_E5, NONE), // DEVSLP1
+	PAD_NC(GPP_E6, NONE), // PCH_GPP_E6 strap
+	_PAD_CFG_STRUCT(GPP_E7, 0x82840100, 0x0000), // SMI#
+	PAD_NC(GPP_E8, NONE),
+	PAD_NC(GPP_E9, NONE),
+	PAD_NC(GPP_E10, NONE), // THC0_SPI1 chip select
+	PAD_NC(GPP_E11, NONE), // THC0_SPI1 clock
+	PAD_NC(GPP_E12, NONE),
+	PAD_NC(GPP_E13, NONE),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE), // ALERT#
+	PAD_CFG_GPI(GPP_E16, DN_20K, DEEP), // SB_KBCRST#
+	PAD_NC(GPP_E17, NONE),
+	PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016
+	PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016
+	PAD_NC(GPP_E20, NONE), // SWI#
+	PAD_NC(GPP_E21, NONE), // DDP2 I2C / TBT_LSX1 strap
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_NC(GPP_F4, NONE),
+	PAD_NC(GPP_F5, NONE),
+	PAD_NC(GPP_F6, NONE), // CNVI_GNSS_PA_BLANKING
+	PAD_CFG_GPO(GPP_F7, 1, DEEP), // GPIO_LANRTD3
+	PAD_NC(GPP_F8, NONE),
+	PAD_CFG_GPO(GPP_F9, 1, DEEP), // GPIO_LAN_EN
+	PAD_NC(GPP_F10, NONE), // strap
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_CFG_GPI(GPP_F17, NONE, PLTRST), // TPM_DET#
+	PAD_NC(GPP_F18, NONE),
+	PAD_NC(GPP_F19, NONE),
+	PAD_NC(GPP_F20, NONE), // EXT_PWR_GATE1#
+	PAD_CFG_GPI(GPP_F21, DN_20K, DEEP), // EXT_PWR_GATE#
+	PAD_NC(GPP_F22, NONE), // VNN_CTRL
+	PAD_NC(GPP_F23, NONE), // 1P05_CTRL
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST), // boot config strap, bit 1
+	PAD_NC(GPP_H1, NONE), // boot config strap, bit 2
+	PAD_NC(GPP_H2, NONE), // boot config strap, bit 3
+	PAD_NC(GPP_H3, NONE),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // GPPH_I2C2_SDA
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // GPPH_I2C2_SCL
+	PAD_NC(GPP_H6, NONE),
+	PAD_NC(GPP_H7, NONE), // SWI#
+	PAD_CFG_GPI(GPP_H8, DN_20K, DEEP), // CNVI_MFUART2_RXD
+	PAD_CFG_GPI(GPP_H9, DN_20K, DEEP), // CNVI_MFUART2_TXD
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // SSD0_CLKREQ#
+	PAD_NC(GPP_H11, NONE),
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H19, NONE), // CNVI_WAKE#
+	PAD_NC(GPP_H20, NONE), // PM_CLKRUN#
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_NC(GPP_H23, NONE),
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE), // ALERT#
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE), // GPPC_DMIC_CLK
+	PAD_NC(GPP_S7, NONE), // GPPC_DMIC_DATA
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+
+	/* ------- GPIO Group GPP_U ------- */
+	PAD_CFG_GPO(GPP_U4, 0, PLTRST), // GPIO_SDCARD_EN
+	PAD_CFG_GPO(GPP_U5, 1, PLTRST), // SDCARD_WAKE#
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/darp7/gpio_early.c b/src/mainboard/system76/darp7/gpio_early.c
new file mode 100644
index 0000000000..80f37c6553
--- /dev/null
+++ b/src/mainboard/system76/darp7/gpio_early.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/darp7/hda_verb.c b/src/mainboard/system76/darp7/hda_verb.c
new file mode 100644
index 0000000000..dc5f72e5d8
--- /dev/null
+++ b/src/mainboard/system76/darp7/hda_verb.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC293 */
+	0x10ec0293, /* Vendor ID */
+	0x155851a1, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155851a1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40738205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/darp7/include/mainboard/gpio.h b/src/mainboard/system76/darp7/include/mainboard/gpio.h
new file mode 100644
index 0000000000..c6393beebb
--- /dev/null
+++ b/src/mainboard/system76/darp7/include/mainboard/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_configure_early_gpios(void);
+void mainboard_configure_gpios(void);
+
+#endif
diff --git a/src/mainboard/system76/darp7/ramstage.c b/src/mainboard/system76/darp7/ramstage.c
new file mode 100644
index 0000000000..a3b12bb1f2
--- /dev/null
+++ b/src/mainboard/system76/darp7/ramstage.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/ramstage.h>
+
+static void mainboard_init(void *chip_info)
+{
+	mainboard_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};
diff --git a/src/mainboard/system76/darp7/romstage.c b/src/mainboard/system76/darp7/romstage.c
new file mode 100644
index 0000000000..a72b647d37
--- /dev/null
+++ b/src/mainboard/system76/darp7/romstage.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/util.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR4,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated);
+}