diff options
| author | John Su <john_su@compal.corp-partner.google.com> | 2022-02-16 13:33:05 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-18 14:57:44 +0000 |
| commit | 41994fee94d8130123006b925255e623a5294c3a (patch) | |
| tree | 5c17316165cfac036695bed6aa1bec049ba9248c /src | |
| parent | d91a6842bfb718779125920318a7b632d58506b0 (diff) | |
mb/google/brya/var/felwinter: Update DPTF parameters for Felwinter
Follow thermal team design to remove TSR3 sensor and update thermal
table for next build. The DPTF parameters were verified by thermal
team.
BUG=b:219690502
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I0e34fabe546b6eabb3d3adad583668a15a1d908b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/felwinter/overridetree.cb | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index f25817a2c3..1bde55c9b9 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -78,28 +78,27 @@ chip soc/intel/alderlake register "options.tsr[0].desc" = ""DRAM_SOC"" register "options.tsr[1].desc" = ""Ambient"" register "options.tsr[2].desc" = ""Charger"" - register "options.tsr[3].desc" = ""WWAN"" ## Active Policy register "policies.active" = "{ [0] = { .target = DPTF_CPU, .thresholds = { - TEMP_PCT(55, 65), - TEMP_PCT(52, 59), - TEMP_PCT(49, 50), - TEMP_PCT(46, 43), - TEMP_PCT(43, 37), + TEMP_PCT(44, 76), + TEMP_PCT(40, 65), + TEMP_PCT(36, 53), + TEMP_PCT(32, 41), + TEMP_PCT(28, 29), } }, [1] = { .target = DPTF_TEMP_SENSOR_1, .thresholds = { - TEMP_PCT(55, 65), - TEMP_PCT(52, 59), - TEMP_PCT(49, 50), - TEMP_PCT(46, 43), - TEMP_PCT(43, 37), + TEMP_PCT(44, 76), + TEMP_PCT(40, 65), + TEMP_PCT(36, 53), + TEMP_PCT(32, 41), + TEMP_PCT(28, 29), } } }" @@ -110,7 +109,6 @@ chip soc/intel/alderlake [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), - [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), }" ## Critical Policy @@ -119,7 +117,6 @@ chip soc/intel/alderlake [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), - [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), }" register "controls.power_limits" = "{ |