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authorSean Rhodes <sean@starlabs.systems>2022-05-19 22:02:48 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-09-01 14:18:19 +0000
commit412222ae75d1743a78d2b745754431a558f31be8 (patch)
tree15f06d984b40dcc4778325008c010216b29f913b /src
parent234c42f7ed0ad15cbe3b5627d74b689551130bd6 (diff)
vendorcode/intel/fsp2/glk: Add the FSP headers for version 2.2.3.1
Add the headers for 2.2.3.1, which includes the following changes over 2.2.0.0: • [Implemented]GLK: XHCLKGTEN Register setting causes S0ix entry failure in less than 5 cycles when a USB2 Ethernet Dongle is connected. Refer GLK BIOS Spec Volume1 CDI# 571118 under chapter 7.20.6 for new Register settings. • [Implemented] [GLK/GLK-R] DDR4 16Gb SDP Memory support for Gemini Lake/Gemini Lake – R • [Update] MRC new version update to 1.38. • [Fixed][GLK-R][WLAN] Removed the DSW function - Wake on LAN from S4 issue with latest Wifi driver. [Update] MRC new version update to 1.39. Included fix for MinRefRate2xEnable and support for Rowhammer mitigation. • [Fixed] Disable Dynamic DiffAmp and set CTLE from 7 to 5. This change specific to DDR4 memory configuration. • GLK Klocwork Fix • [Update] MRC new version update to 1.40. Added in a separate directory as the default. The 2.2.0.0 headers were left and will be used for Google boards, as some offsets have moved. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I09498368b116c2add816eeada2fa4d0dba6e5765 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/Kconfig3
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/glk/2.2.0.0/FspUpd.h (renamed from src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h)0
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/glk/2.2.0.0/FspmUpd.h (renamed from src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h)0
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/glk/2.2.0.0/FspsUpd.h (renamed from src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h)0
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1/FspUpd.h48
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1/FspmUpd.h1032
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1/FspsUpd.h1832
7 files changed, 2914 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index dc8df20767..c63f4fda0d 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -209,7 +209,8 @@ config VERSTAGE_ADDR
The base address (in CAR) where verstage should be linked
config FSP_HEADER_PATH
- default "src/vendorcode/intel/fsp/fsp2_0/glk" if SOC_INTEL_GEMINILAKE
+ default "src/vendorcode/intel/fsp/fsp2_0/glk/2.2.0.0" if VENDOR_GOOGLE && SOC_INTEL_GEMINILAKE
+ default "src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1" if SOC_INTEL_GEMINILAKE
default "3rdparty/fsp/ApolloLakeFspBinPkg/Include/"
config FSP_FD_PATH
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.0.0/FspUpd.h
index 20bd9afe1b..20bd9afe1b 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.0.0/FspUpd.h
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.0.0/FspmUpd.h
index 0329c939c0..0329c939c0 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.0.0/FspmUpd.h
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.0.0/FspsUpd.h
index 0d3902db48..0d3902db48 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.0.0/FspsUpd.h
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1/FspUpd.h
new file mode 100644
index 0000000000..bf55ada7c5
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1/FspUpd.h
@@ -0,0 +1,48 @@
+/** @file
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE 0x545F4450554B4C47 /* 'GLKUPD_T' */
+
+#define FSPM_UPD_SIGNATURE 0x4D5F4450554B4C47 /* 'GLKUPD_M' */
+
+#define FSPS_UPD_SIGNATURE 0x535F4450554B4C47 /* 'GLKUPD_S' */
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1/FspmUpd.h
new file mode 100644
index 0000000000..fae29ff458
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1/FspmUpd.h
@@ -0,0 +1,1032 @@
+/** @file
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+#define MAX_NODE_NUM 1
+#define MAX_CHANNELS_NUM 4
+#define MAX_DIMMS_NUM 1
+
+#define MAX_PROFILE_NUM 4 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 29
+#endif
+
+#define MRC_DDR_TYPE_LPDDR4 6
+#define MRC_DDR_TYPE_DDR4 7
+
+//
+// MRC version description.
+//
+typedef struct {
+ UINT8 Major; ///< Major version number
+ UINT8 Minor; ///< Minor version number
+ UINT8 Rev; ///< Revision number
+ UINT8 Build; ///< Build number
+} SiMrcVersion;
+
+//
+// DIMM timings
+//
+typedef struct {
+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
+} MRC_CH_TIMING;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
+ UINT8 DimmId;
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth;///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this channel should be used.
+ UINT8 ChannelId;
+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+ DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; ///< Save the DIMM output characteristics.
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
+ CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; ///< The following are channel level definitions.
+} CONTROLLER_INFO;
+
+typedef struct {
+ UINT8 Revision;
+ UINT16 DataWidth; ///< Data width, in bits, of this memory device
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+
+ SiMrcVersion Version;
+ BOOLEAN EccSupport;
+ UINT8 MemoryProfile;
+ UINT32 TotalPhysicalMemorySize;
+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ UINT8 Ratio;
+ UINT8 RefClk;
+ UINT32 VddVoltage[MAX_PROFILE_NUM];
+ CONTROLLER_INFO Controller[MAX_NODE_NUM];
+} FSP_SMBIOS_MEMORY_INFO;
+
+typedef struct {
+ UINT16 TotalNumberOfSockets;
+ UINT16 CurrentSocketNumber;
+ UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.1
+ /** This info is used for both ProcessorFamily and ProcessorFamily2 fields
+ See ENUM defined in SMBIOS Spec v3.0 Section 7.5.2
+ **/
+ UINT16 ProcessorFamily;
+ UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
+ UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.3
+ UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
+ UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.4
+ UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
+ UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
+ UINT8 Status; ///< Format defined in the SMBIOS Spec v3.0 Table 21
+ UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.5
+ /** This info is used for both CoreCount & CoreCount2 fields
+ See detailed description in SMBIOS Spec v3.0 Section 7.5.6
+ **/
+ UINT16 CoreCount;
+ /** This info is used for both CoreEnabled & CoreEnabled2 fields
+ See detailed description in SMBIOS Spec v3.0 Section 7.5.7
+ **/
+ UINT16 EnabledCoreCount;
+ /** This info is used for both ThreadCount & ThreadCount2 fields
+ See detailed description in SMBIOS Spec v3.0 Section 7.5.8
+ **/
+ UINT16 ThreadCount;
+ UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.9
+ /**
+ String Buffer - each string terminated by NULL "0x00"
+ String buffer terminated by double NULL "0x0000"
+ **/
+} FSP_SMBIOS_PROCESSOR_INFO;
+
+typedef struct {
+ UINT16 ProcessorSocketNumber;
+ UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
+ UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
+ UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.0 Section7.8 Table36
+ UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
+ UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
+ UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
+ UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
+ UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
+ UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.3
+ UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.4
+ UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.5
+ /**
+ String Buffer - each string terminated by NULL "0x00"
+ String buffer terminated by double NULL "0x0000"
+ **/
+} FSP_SMBIOS_CACHE_INFO;
+
+
+/** Fsp M Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Debug Serial Port Base address
+ Debug serial port base address. This option will be used only when the 'Serial Port
+ Debug Device' option is set to 'External Device'. 0x00000000(Default).
+**/
+ UINT32 SerialDebugPortAddress;
+
+/** Offset 0x0044 - Debug Serial Port Type
+ 16550 compatible debug serial port resource type. NONE means no serial port support.
+ 0x02:MMIO(Default).
+ 0:NONE, 1:I/O, 2:MMIO
+**/
+ UINT8 SerialDebugPortType;
+
+/** Offset 0x0045 - Serial Port Debug Device
+ Select active serial port device for debug. For SOC UART devices,'Debug Serial Port
+ Base' options will be ignored. 0x02:SOC UART2(Default).
+ 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device
+**/
+ UINT8 SerialDebugPortDevice;
+
+/** Offset 0x0046 - Debug Serial Port Stride Size
+ Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default).
+ 0:1, 2:4
+**/
+ UINT8 SerialDebugPortStrideSize;
+
+/** Offset 0x0047 - Memory Fast Boot
+ Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 MrcFastBoot;
+
+/** Offset 0x0048 - Integrated Graphics Device
+ Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video
+ Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 Igd;
+
+/** Offset 0x0049 - DVMT Pre-Allocated
+ Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal
+ Graphics Device. 0x02:64 MB(Default).
+ 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256
+ MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB,
+ 0x0F:480 MB, 0x10:512 MB
+**/
+ UINT8 IgdDvmt50PreAlloc;
+
+/** Offset 0x004A - Aperture Size
+ Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default),
+ 0x2:256 MB, 0x3:512 MB.
+ 0x1:128 MB, 0x2:256 MB, 0x3:512 MB
+**/
+ UINT8 IgdApertureSize;
+
+/** Offset 0x004B - GTT Size
+ Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8
+ MB(Default).
+ 0x1:2 MB, 0x2:4 MB, 0x3:8 MB
+**/
+ UINT8 GttSize;
+
+/** Offset 0x004C - Primary Display
+ Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default),
+ 0x2:IGD, 0x3:PCI
+ 0x0:AUTO, 0x2:IGD, 0x3:PCI
+**/
+ UINT8 PrimaryVideoAdaptor;
+
+/** Offset 0x004D - Package
+ NOTE: Specifies CA Mapping for all technologies. Supported CA Mappings: 0 - SODIMM(Default);
+ 1 - BGA; 2 - BGA mirrored (LPDDR3 only); 3 - SODIMM/UDIMM with Rank 1 Mirrored
+ (DDR3L); Refer to the IAFW spec for specific details about each CA mapping.
+ 0x0:SODIMM, 0x1:BGA, 0x2:BGA mirrored (LPDDR3 only), 0x3:SODIMM/UDIMM with Rank
+ 1 Mirrored (DDR3L)
+**/
+ UINT8 Package;
+
+/** Offset 0x004E - Profile
+ Profile list. 0x15(Default).
+ 0x01:LPDDR3_1333_10_12_12, 0x02:LPDDR3_1600_12_15_15, 0x03:LPDDR3_1866_14_17_17,
+ 0x04:LPDDR4_1600_14_15_15, 0x05:LPDDR4_1866_20_17_17, 0x06:LPDDR4_2133_20_20_20,
+ 0x07:LPDDR4_2400_24_22_22, 0x08:LPDDR4_2666_24_24_24, 0x09:LPDDR4_3200_28_29_29,
+ 0x0A:DDR4_1600_10_10_10, 0x0B:DDR4_1600_11_11_11, 0x0C:DDR4_1600_12_12_12, 0x0D:DDR4_1866_12_12_12,
+ 0x0E:DDR4_1866_13_13_13, 0x0F:DDR4_1866_14_14_14, 0x10:DDR4_2133_14_14_14, 0x11:DDR4_2133_15_15_15,
+ 0x12:DDR4_2133_16_16_16, 0x13:DDR4_2400_15_15_15, 0x14:DDR4_2400_16_16_16, 0x15:DDR4_2400_17_17_17,
+ 0x16:DDR4_2400_18_18_18, 0x17:DDR4_2666_17_17_17, 0x18:DDR4_2666_18_18_18, 0x19:DDR4_2666_19_19_19,
+ 0x1A:DDR4_2666_20_20_20
+**/
+ UINT8 Profile;
+
+/** Offset 0x004F - MemoryDown
+ Memory Down. 0x0(Default).
+ 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L/4 only) ACRD, 0x3:1x32 LPDDR4
+**/
+ UINT8 MemoryDown;
+
+/** Offset 0x0050 - DDR3LPageSize
+ NOTE: Only for memory down (soldered down memory with no SPD). 0x01:1KB(Default), 0x02:2KB.
+ 0x1:1KB, 0x2:2KB
+**/
+ UINT8 DDR3LPageSize;
+
+/** Offset 0x0051 - DDR3LASR
+ NOTE: Only for memory down. This is specific to ddr3l and used for refresh adjustment
+ in Self Refresh, does not affect LP4. 0x00:Not Supported(Default), 0x01:Supported.
+ 0x0:Not Supported, 0x1:Supported
+**/
+ UINT8 DDR3LASR;
+
+/** Offset 0x0052 - ScramblerSupport
+ Scrambler Support - Enable or disable the memory scrambler. Data scrambling is
+ provided as a means to increase signal integrity/reduce RFI generated by the DRAM
+ interface. This is achieved by randomizing seed that encodes/decodes memory data
+ so repeating a worse case pattern is hard to repeat. 00: Disable Scrambler Support,
+ 01: Enable Scrambler Support
+ $EN_DIS
+**/
+ UINT8 ScramblerSupport;
+
+/** Offset 0x0053 - InterleavedMode
+ This field is ignored if one of the PnP channel configurations is used. If the memory
+ configuration is different, then the field is used directly to populate. 0x00:Disable(Default),
+ 0x02:Enable.
+ 0x0:Disable, 0x2:Enable
+**/
+ UINT8 InterleavedMode;
+
+/** Offset 0x0054 - ChannelHashMask
+ ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be
+ modified. These inputs are not used for configurations where an optimized ChannelHashMask
+ has been provided by the PnP validation teams. 0x00(Default).
+**/
+ UINT16 ChannelHashMask;
+
+/** Offset 0x0056 - SliceHashMask
+ ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be
+ modified. These inputs are not used for configurations where an optimized ChannelHashMask
+ has been provided by the PnP validation teams. 0x00(Default).
+**/
+ UINT16 SliceHashMask;
+
+/** Offset 0x0058 - ChannelsSlicesEnable
+ ChannelSlicesEnable field is not used at all on BXTP. The Channel Slice Configuration
+ is calculated internally based on the enabled channel configuration. 0x00:Disable(Default),
+ 0x01:Enable.
+ $EN_DIS
+**/
+ UINT8 ChannelsSlicesEnable;
+
+/** Offset 0x0059 - MinRefRate2xEnable
+ Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default),
+ 0x01:Enable.
+ $EN_DIS
+**/
+ UINT8 MinRefRate2xEnable;
+
+/** Offset 0x005A - DualRankSupportEnable
+ Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 DualRankSupportEnable;
+
+/** Offset 0x005B - RmtMode
+ Rank Margin Tool Mode. 0x00(Default), 0x3(Enabled).
+ 0x0:Disabled, 0x3:Enabled
+**/
+ UINT8 RmtMode;
+
+/** Offset 0x005C - MemorySizeLimit
+ Memory Size Limit: This value is used to restrict the total amount of memory and
+ the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB,
+ 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default)
+**/
+ UINT16 MemorySizeLimit;
+
+/** Offset 0x005E - LowMemoryMaxValue
+ Low Memory Max Value: This value is used to restrict the amount of memory below
+ 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400
+ = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default).
+**/
+ UINT16 LowMemoryMaxValue;
+
+/** Offset 0x0060 - HighMemoryMaxValue
+ High Memory Max Value: This value is used to restrict the amount of memory above
+ 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB,
+ 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default).
+**/
+ UINT16 HighMemoryMaxValue;
+
+/** Offset 0x0062 - DisableFastBoot
+ 00:Disabled; Use saved training data (if valid) after first boot(Default), 01:Enabled;
+ Full re-train of memory on every boot.
+ $EN_DIS
+**/
+ UINT8 DisableFastBoot;
+
+/** Offset 0x0063 - DIMM0SPDAddress
+ DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default).
+**/
+ UINT8 DIMM0SPDAddress;
+
+/** Offset 0x0064 - DIMM1SPDAddress
+ DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default).
+**/
+ UINT8 DIMM1SPDAddress;
+
+/** Offset 0x0065 - Ch0_RankEnable
+ NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
+ NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
+ 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
+ set to 1 to enable use of this rank.
+**/
+ UINT8 Ch0_RankEnable;
+
+/** Offset 0x0066 - Ch0_DeviceWidth
+ NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
+ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
+ and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
+ device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
+ 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64
+**/
+ UINT8 Ch0_DeviceWidth;
+
+/** Offset 0x0067 - Ch0_DramDensity
+ NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
+ density per rank (per Chip Select). The simplest way of identifying the density
+ per rank is to divide the total SoC memory channel density by the number of ranks.
+ For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
+ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
+ a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
+ 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved
+ 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb
+**/
+ UINT8 Ch0_DramDensity;
+
+/** Offset 0x0068 - Ch0_Option
+ BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
+ 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
+ Bank Address Hashing Enable. See Address Mapping section for full description:
+ 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
+ CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
+ designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
+ CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
+ specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
+**/
+ UINT8 Ch0_Option;
+
+/** Offset 0x0069 - Ch0_OdtConfig
+ BIT[0] Change the READ ODT strength, for SOC termination during a READ transaction,
+ ON DQ BITs: 0 - WEAK_ODT_CONFIG (default); 1 - STRONG_ODT_CONFIG; BIT[4:1] - Reserved;
+ BIT[5] nWR config: 0 - nWR6; 1 - nWR24 (default); BIT[31:6] - Reserved
+**/
+ UINT8 Ch0_OdtConfig;
+
+/** Offset 0x006A - Ch0_TristateClk1
+ Not used
+**/
+ UINT8 Ch0_TristateClk1;
+
+/** Offset 0x006B - Ch0_Mode2N
+ DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
+ mode that provides more setup and hold time for DRAM commands on the DRAM command
+ bus. This is useful for platforms with unusual CMD bus routing or marginal signal
+ integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
+ Control training), 1 - Force 2N Mode
+ 0x0:Auto, 0x1:Force 2N CMD Timing Mode
+**/
+ UINT8 Ch0_Mode2N;
+
+/** Offset 0x006C - Ch0_OdtLevels
+ Parameter used to determine if ODT will be held high or low: 0 - ODT Connected to
+ SoC, 1 - ODT held high
+**/
+ UINT8 Ch0_OdtLevels;
+
+/** Offset 0x006D - Ch1_RankEnable
+ NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
+ NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
+ 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
+ set to 1 to enable use of this rank.
+**/
+ UINT8 Ch1_RankEnable;
+
+/** Offset 0x006E - Ch1_DeviceWidth
+ NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
+ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
+ and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
+ device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
+ 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64
+**/
+ UINT8 Ch1_DeviceWidth;
+
+/** Offset 0x006F - Ch1_DramDensity
+ NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
+ density per rank (per Chip Select). The simplest way of identifying the density
+ per rank is to divide the total SoC memory channel density by the number of ranks.
+ For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
+ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
+ a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
+ 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved
+ 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb
+**/
+ UINT8 Ch1_DramDensity;
+
+/** Offset 0x0070 - Ch1_Option
+ BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
+ 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
+ Bank Address Hashing Enable. See Address Mapping section for full description:
+ 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
+ CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
+ designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
+ CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
+ specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
+**/
+ UINT8 Ch1_Option;
+
+/** Offset 0x0071 - Ch1_OdtConfig
+ BIT[0] Change the READ ODT strength, for SOC termination during a READ transaction,
+ ON DQ BITs: 0 - WEAK_ODT_CONFIG (default); 1 - STRONG_ODT_CONFIG; BIT[4:1] - Reserved;
+ BIT[5] nWR config: 0 - nWR6; 1 - nWR24 (default); BIT[31:6] - Reserved
+**/
+ UINT8 Ch1_OdtConfig;
+
+/** Offset 0x0072 - Ch1_TristateClk1
+ Not used
+**/
+ UINT8 Ch1_TristateClk1;
+
+/** Offset 0x0073 - Ch1_Mode2N
+ DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
+ mode that provides more setup and hold time for DRAM commands on the DRAM command
+ bus. This is useful for platforms with unusual CMD bus routing or marginal signal
+ integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
+ Control training), 1 - Force 2N Mode
+ 0x0:Auto, 0x1:Force 2N CMD Timing Mode
+**/
+ UINT8 Ch1_Mode2N;
+
+/** Offset 0x0074 - Ch1_OdtLevels
+ DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW
+ (default), 1 - ODT_AB_HIGH_HIGH
+**/
+ UINT8 Ch1_OdtLevels;
+
+/** Offset 0x0075 - Ch2_RankEnable
+ NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
+ NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
+ 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
+ set to 1 to enable use of this rank.
+**/
+ UINT8 Ch2_RankEnable;
+
+/** Offset 0x0076 - Ch2_DeviceWidth
+ NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
+ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
+ and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
+ device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
+ 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64
+**/
+ UINT8 Ch2_DeviceWidth;
+
+/** Offset 0x0077 - Ch2_DramDensity
+ NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
+ density per rank (per Chip Select). The simplest way of identifying the density
+ per rank is to divide the total SoC memory channel density by the number of ranks.
+ For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
+ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
+ a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
+ 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved
+ 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb
+**/
+ UINT8 Ch2_DramDensity;
+
+/** Offset 0x0078 - Ch2_Option
+ BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
+ 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
+ Bank Address Hashing Enable. See Address Mapping section for full description:
+ 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
+ CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
+ designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
+ CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
+ specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
+**/
+ UINT8 Ch2_Option;
+
+/** Offset 0x0079 - Ch2_OdtConfig
+ BIT[0] Change the READ ODT strength, for SOC termination during a READ transaction,
+ ON DQ BITs: 0 - WEAK_ODT_CONFIG (default); 1 - STRONG_ODT_CONFIG; BIT[4:1] - Reserved;
+ BIT[5] nWR config: 0 - nWR6; 1 - nWR24 (default); BIT[31:6] - Reserved
+**/
+ UINT8 Ch2_OdtConfig;
+
+/** Offset 0x007A - Ch2_TristateClk1
+ Not used
+**/
+ UINT8 Ch2_TristateClk1;
+
+/** Offset 0x007B - Ch2_Mode2N
+ DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
+ mode that provides more setup and hold time for DRAM commands on the DRAM command
+ bus. This is useful for platforms with unusual CMD bus routing or marginal signal
+ integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
+ Control training), 1 - Force 2N Mode
+ 0x0:Auto, 0x1:Force 2N CMD Timing Mode
+**/
+ UINT8 Ch2_Mode2N;
+
+/** Offset 0x007C - Ch2_OdtLevels
+ DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW
+ (default), 1 - ODT_AB_HIGH_HIGH
+**/
+ UINT8 Ch2_OdtLevels;
+
+/** Offset 0x007D - Ch3_RankEnable
+ NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
+ NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
+ 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
+ set to 1 to enable use of this rank.
+**/
+ UINT8 Ch3_RankEnable;
+
+/** Offset 0x007E - Ch3_DeviceWidth
+ NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
+ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
+ and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
+ device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
+ 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64
+**/
+ UINT8 Ch3_DeviceWidth;
+
+/** Offset 0x007F - Ch3_DramDensity
+ NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
+ density per rank (per Chip Select). The simplest way of identifying the density
+ per rank is to divide the total SoC memory channel density by the number of ranks.
+ For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
+ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
+ a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
+ 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved
+ 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb
+**/
+ UINT8 Ch3_DramDensity;
+
+/** Offset 0x0080 - Ch3_Option
+ BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
+ 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
+ Bank Address Hashing Enable. See Address Mapping section for full description:
+ 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
+ CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
+ designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
+ CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
+ specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
+**/
+ UINT8 Ch3_Option;
+
+/** Offset 0x0081 - Ch3_OdtConfig
+ BIT[0] Change the READ ODT strength, for SOC termination during a READ transaction,
+ ON DQ BITs: 0 - WEAK_ODT_CONFIG (default); 1 - STRONG_ODT_CONFIG; BIT[4:1] - Reserved;
+ BIT[5] nWR config: 0 - nWR6; 1 - nWR24 (default); BIT[31:6] - Reserved
+**/
+ UINT8 Ch3_OdtConfig;
+
+/** Offset 0x0082 - Ch3_TristateClk1
+ Not used
+**/
+ UINT8 Ch3_TristateClk1;
+
+/** Offset 0x0083 - Ch3_Mode2N
+ DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
+ mode that provides more setup and hold time for DRAM commands on the DRAM command
+ bus. This is useful for platforms with unusual CMD bus routing or marginal signal
+ integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
+ Control training), 1 - Force 2N Mode
+ 0x0:Auto, 0x1:Force 2N CMD Timing Mode
+**/
+ UINT8 Ch3_Mode2N;
+
+/** Offset 0x0084 - Ch3_OdtLevels
+ DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW
+ (default), 1 - ODT_AB_HIGH_HIGH
+**/
+ UINT8 Ch3_OdtLevels;
+
+/** Offset 0x0085 - RmtCheckRun
+ Parameter used to determine whether to run the margin check. Bit 0 is used for MINIMUM
+ MARGIN CHECK and bit 1 is used for DEGRADE MARGIN CHECK
+**/
+ UINT8 RmtCheckRun;
+
+/** Offset 0x0086 - RmtMarginCheckScaleHighThreshold
+ Percentage used to determine the margin tolerances over the failing margin.
+**/
+ UINT16 RmtMarginCheckScaleHighThreshold;
+
+/** Offset 0x0088 - Ch0_Bit_swizzling
+ Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. Frequently
+ asked questions: Q: The DQS (strobes) need to go with the corresponding byte lanes
+ on the DDR module. Are the DQS being swapped around as well? Ans: Yes, DQ strobes
+ need to follow the DQ byte lane they correspond too. So for example if you have
+ DQ[7:0] swapped with DQ[15:8], DQS0 pair also need to be swapped with DQS1 pair.
+ Also, the spreadsheet used for Amenia is essentially a swizzle value lookup that
+ specifies what DRAM DQ bit a particular SoC DQ bit is connected to. Some confusion
+ can arrise from the fact that the indexes to the array do not necessarily map 1:1
+ to an SoC DQ pin. For example, the CH0 array at index 0 maps to SoC DQB8. The value
+ of 9 at index 0 tells us that SoC DQB8 is connected to DRAM DQA9. Q: The PDG indicates
+ a 2 physical channels need to be stuffed and operated together. Are the CHx_A and
+ CHx_B physical channels operated in tandem or completely separate? If separate,
+ why requirement of pairing them? Ans: We have 2 PHY instances on the SoC each supporting
+ up to 2 x32 LP4 channels. If you have 4 channels both PHYs are active, but if you
+ have 2 channels in order to power gate one PHY, those two channel populated must
+ be on one PHY instance. So yes all channels are independent of each other, but
+ there are some restrictions on how they need to be populated. Q: How is it that
+ an LPDDR4 device is identified as having a x16 width when all 32-bits are used
+ at the same time with a single chip select? That's effectively a x32 device. Ans:LPDDR4
+ DRAM devices are x16. Each die has 2 x16 devices on them. To make a x32 channel
+ the CS of the two devices in the same die are connected together to make a single
+ rank of one x32 channel (SDP). The second die in the DDP package makes the second rank.
+**/
+ UINT8 Ch0_Bit_swizzling[32];
+
+/** Offset 0x00A8 - Ch1_Bit_swizzling
+ Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
+**/
+ UINT8 Ch1_Bit_swizzling[32];
+
+/** Offset 0x00C8 - Ch2_Bit_swizzling
+ Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
+**/
+ UINT8 Ch2_Bit_swizzling[32];
+
+/** Offset 0x00E8 - Ch3_Bit_swizzling
+ Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
+**/
+ UINT8 Ch3_Bit_swizzling[32];
+
+/** Offset 0x0108 - MsgLevelMask
+ 32 bits used to mask out debug messages. Masking out bit 0 mask all other messages.
+**/
+ UINT32 MsgLevelMask;
+
+/** Offset 0x010C
+**/
+ UINT8 UnusedUpdSpace0[4];
+
+/** Offset 0x0110 - PreMem GPIO Pin Number for each table
+ Number of Pins in each PreMem GPIO Table. 0(Default).
+**/
+ UINT8 PreMemGpioTablePinNum[4];
+
+/** Offset 0x0114 - PreMem GPIO Table Pointer
+ Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default).
+**/
+ UINT32 PreMemGpioTablePtr;
+
+/** Offset 0x0118 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4
+ Number of Entries in PreMem GPIO Table. 0(Default).
+**/
+ UINT8 PreMemGpioTableEntryNum;
+
+/** Offset 0x0119 - Enhance the port 8xh decoding
+ Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 EnhancePort8xhDecoding;
+
+/** Offset 0x011A - SPD Data Write
+ Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable.
+ $EN_DIS
+**/
+ UINT8 SpdWriteEnable;
+
+/** Offset 0x011B - MRC Training Data Saving
+ Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable.
+ $EN_DIS
+**/
+ UINT8 MrcDataSaving;
+
+/** Offset 0x011C - OEM File Loading Address
+ Determine the memory base address to load a specified file from CSE file system
+ after memory is available.
+**/
+ UINT32 OemLoadingBase;
+
+/** Offset 0x0120
+**/
+ UINT8 Reserved[16];
+
+/** Offset 0x0130
+**/
+ VOID* MrcBootDataPtr;
+
+/** Offset 0x0134 - eMMC Trace Length
+ Select eMMC trace length to load OEM file from when loading OEM file name is specified.
+ 0x0:Long(Default), 0x1:Short.
+ 0x0:Long, 0x1:Short
+**/
+ UINT8 eMMCTraceLen;
+
+/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB
+ Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of
+ CSE. 0x00:Disable(Default), 0x01:Enable.
+ $EN_DIS
+**/
+ UINT8 SkipCseRbp;
+
+/** Offset 0x0136 - Trace Hub Enable
+ Disable Npk/Host Debugger/Target Debugger. 0:Disable(Default), 1:Host Debugger,
+ 2:Target Debugger.
+ 0:Disable, 1:Host Debugger, 2:Target Debugger
+**/
+ UINT8 TraceHubEn;
+
+/** Offset 0x0137 - FW Trace Enable
+ Enable/Disable FW Trace. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 FwTraceEn;
+
+/** Offset 0x0138 - FW Trace Destination
+ FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB,
+ 4-NPK_TRACE_TO_PTI(Default).
+**/
+ UINT8 FwTraceDestination;
+
+/** Offset 0x0139 - NPK Recovery Dump
+ Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 RecoverDump;
+
+/** Offset 0x013A - Memory Region 0 Buffer WrapAround
+ Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
+**/
+ UINT8 Msc0Wrap;
+
+/** Offset 0x013B - Memory Region 1 Buffer WrapAround
+ Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
+**/
+ UINT8 Msc1Wrap;
+
+/** Offset 0x013C - Memory Region 0 Buffer Size
+ Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
+ 6-512MB, 7-1GB.
+**/
+ UINT32 Msc0Size;
+
+/** Offset 0x0140 - Memory Region 1 Buffer Size
+ Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
+ 6-512MB, 7-1GB.
+**/
+ UINT32 Msc1Size;
+
+/** Offset 0x0144 - PTI Mode
+ PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16.
+**/
+ UINT8 PtiMode;
+
+/** Offset 0x0145 - PTI Training
+ PTI Training. 0-off(Default), 1-6=1-6.
+**/
+ UINT8 PtiTraining;
+
+/** Offset 0x0146 - PTI Speed
+ PTI Speed. 0-full, 1-half, 2-quarter(Default).
+**/
+ UINT8 PtiSpeed;
+
+/** Offset 0x0147 - Punit Message Level
+ Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
+**/
+ UINT8 PunitMlvl;
+
+/** Offset 0x0148 - PMC Message Level
+ PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
+**/
+ UINT8 PmcMlvl;
+
+/** Offset 0x0149 - SW Trace Enable
+ Enable/Disable SW Trace. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 SwTraceEn;
+
+/** Offset 0x014A - SGX mode
+ Select SGX mode. 0:Disable, 1:Enable, 2:Software control (default)
+ 0:Disable, 1:Enable, 2:Software control (default)
+**/
+ UINT8 EnableSgx;
+
+/** Offset 0x014B - Periodic Retraining Disable
+ Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic
+ Retraining for debug purposes. Periodic Retraining should be enabled in production.
+ Periodic retraining allows the platform to operate reliably over a larger voltage
+ and temperature range. This field has no effect for DDR3L and LPDDR3 memory type
+ configurations. 0x00: Enable Periodic Retraining (default); 0x01: Disable Periodic
+ Retraining (debug configuration only)
+ 0x0:Enabled, 0x1:Disabled
+**/
+ UINT8 PeriodicRetrainingDisable;
+
+/** Offset 0x014C - PRMRR size
+ PRMRR size. 0:Invalid (default), 1:32MB, 2:64MB 3:128MB
+ 0:Invalid (default), 1:32MB, 2:64MB 3:128MB
+**/
+ UINT32 PrmrrSize;
+
+/** Offset 0x0150 - Enable Reset System
+ Enable FSP to trigger reset instead of returning reset request. 0x00: Return the
+ Return Status from FSP if a reset is required. (default); 0x01: Perform Reset inside
+ FSP instead of returning from the API.
+ 0x0:Disabled, 0x1:Eabled
+**/
+ UINT8 EnableResetSystem;
+
+/** Offset 0x0151 - Enable HECI2 in S3 resume path
+ Enable HECI2 in S3 resume path. 0x00: Skip HECI2 initialization in S3 resume. ;
+ 0x01: Enable HECI2 in S3 resume path.(Default)
+ 0x0:Disabled, 0x1:Eabled
+**/
+ UINT8 EnableS3Heci2;
+
+/** Offset 0x0152 - PCI Express Root Port
+ Control the PCI Express Root Port . 0:Disable, 1:Enable, 2:Auto(Default).
+**/
+ UINT8 PcieRootPortEn[6];
+
+/** Offset 0x0158 - PCIE SLOT Power Enable Assert Time - PFET.
+ ACPI Timer Ticker to measure when PCIE Slot Power is enabled through PFET. FSP will
+ wait for 100ms for the power to be stable, before de-asserting PERST bin. Customer
+ who designed the board PCIE slot Power automatically enabled, can pass value of
+ zero here.
+**/
+ UINT64 StartTimerTickerOfPfetAssert;
+
+/** Offset 0x0160
+**/
+ VOID* VariableNvsBufferPtr;
+
+/** Offset 0x0164 - PERST pin for RootPort 0
+ Address for PERST pin for Rootport 0. For Intel RVP, address of N_GPIO_105. 0x00C507D0(Default).
+**/
+ UINT32 RootPort0Perst;
+
+/** Offset 0x0168 - PERST pin for RootPort 1
+ Address for PERST pin for Rootport 1. For Intel RVP, address of A_GPIO_163. 0x00C90670(Default).
+**/
+ UINT32 RootPort1Perst;
+
+/** Offset 0x016C - PERST pin for RootPort 2
+ Address for PERST pin for Rootport 2. For Intel RVP, address of N_GPIO_137. 0x00C509D0(Default).
+**/
+ UINT32 RootPort2Perst;
+
+/** Offset 0x0170 - PERST pin for RootPort 3
+ Address for PERST pin for Rootport 3.
+**/
+ UINT32 RootPort3Perst;
+
+/** Offset 0x0174 - PERST pin for RootPort 4
+ Address for PERST pin for Rootport 4. For Intel RVP, address of SCC_GPIO_210. 0x00C806D0(Default).
+**/
+ UINT32 RootPort4Perst;
+
+/** Offset 0x0178 - PERST pin for RootPort 5
+ Address for PERST pin for Rootport 5.
+**/
+ UINT32 RootPort5Perst;
+
+/** Offset 0x017C - CpuPeiApWakeupBufferAddr
+ Address for PERST pin for Rootport 5.
+**/
+ UINT32 CpuPeiApWakeupBufferAddr;
+
+/** Offset 0x0180 - SkipPciePowerSequence
+ UPD To Skip PciePowerSequence, set this UPD to 0 by default on windows.
+**/
+ UINT8 SkipPciePowerSequence;
+
+/** Offset 0x0181
+**/
+ UINT8 RevAligmentFspmUpd[7];
+
+/** Offset 0x0188 - SkipMemoryTestUpd
+ UPD To Skip CpuMemoryTest, set this UPD to 0 by default on windows.
+**/
+ UINT8 SkipMemoryTestUpd;
+
+/** Offset 0x0189
+**/
+ UINT8 ReservedFspmUpd[7];
+} FSP_M_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPM_ARCH_UPD FspmArchUpd;
+
+/** Offset 0x0040
+**/
+ FSP_M_CONFIG FspmConfig;
+
+/** Offset 0x0190
+**/
+ UINT8 UnusedUpdSpace1[118];
+
+/** Offset 0x0206
+**/
+ UINT16 UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1/FspsUpd.h
new file mode 100644
index 0000000000..265f1f228d
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1/FspsUpd.h
@@ -0,0 +1,1832 @@
+/** @file
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+/** Fsp S Configuration
+**/
+typedef struct {
+
+/** Offset 0x0020 - ActiveProcessorCores
+ Number of active cores. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 ActiveProcessorCores;
+
+/** Offset 0x0021 - Disable Core1
+ Disable/Enable Core1. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 DisableCore1;
+
+/** Offset 0x0022 - Disable Core2
+ Disable/Enable Core2. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 DisableCore2;
+
+/** Offset 0x0023 - Disable Core3
+ Disable/Enable Core3. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 DisableCore3;
+
+/** Offset 0x0024 - VMX Enable
+ Enable or Disable VMX. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 VmxEnable;
+
+/** Offset 0x0025 - Depricated UPD
+ Depricated UPD
+**/
+ UINT8 Reserved;
+
+/** Offset 0x0026 - Enable Processor Trace
+ Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 ProcessorTraceEnable;
+
+/** Offset 0x0027 - Eist
+ Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 Eist;
+
+/** Offset 0x0028 - Boot PState
+ Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM.
+**/
+ UINT8 BootPState;
+
+/** Offset 0x0029 - CPU power states (C-states)
+ Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 EnableCx;
+
+/** Offset 0x002A - Enhanced C-states
+ Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 C1e;
+
+/** Offset 0x002B - Bi-Directional PROCHOT#
+ Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 BiProcHot;
+
+/** Offset 0x002C - Max Pkg Cstate
+ Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s,
+ 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto.
+**/
+ UINT8 PkgCStateLimit;
+
+/** Offset 0x002D - C-State auto-demotion
+ C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7
+ Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion
+ to C1 and C3.
+**/
+ UINT8 CStateAutoDemotion;
+
+/** Offset 0x002E - C-State un-demotion
+ C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion,
+ 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion.
+**/
+ UINT8 CStateUnDemotion;
+
+/** Offset 0x002F - Max Core C-State
+ Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default).
+**/
+ UINT8 MaxCoreCState;
+
+/** Offset 0x0030 - Package C-State Demotion
+ Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 PkgCStateDemotion;
+
+/** Offset 0x0031 - Package C-State Un-demotion
+ Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 PkgCStateUnDemotion;
+
+/** Offset 0x0032 - Turbo Mode
+ Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 TurboMode;
+
+/** Offset 0x0033 - SC HDA Verb Table Entry Number
+ Number of Entries in Verb Table. 0(Default).
+**/
+ UINT8 HdaVerbTableEntryNum;
+
+/** Offset 0x0034 - SC HDA Verb Table Pointer
+ Pointer to Array of pointers to Verb Table. 0x00000000(Default).
+**/
+ UINT32 HdaVerbTablePtr;
+
+/** Offset 0x0038 - Enable/Disable P2SB device hidden.
+ Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 P2sbUnhide;
+
+/** Offset 0x0039 - IPU Enable/Disable
+ Enable/Disable IPU Device. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 IpuEnReserved;
+
+/** Offset 0x003A - IMGU ACPI mode selection
+ 0:Auto, 1:IGFX Child device(Default), 2:ACPI device.
+ 0:Disable, 1:IGFX Child device, 2:ACPI device
+**/
+ UINT8 IpuAcpiModeReserved;
+
+/** Offset 0x003B - Enable ForceWake
+ Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 ForceWake;
+
+/** Offset 0x003C - GttMmAdr
+ GttMmAdr structure for initialization. 0xBF000000(Default).
+**/
+ UINT32 GttMmAdr;
+
+/** Offset 0x0040 - GmAdr
+ GmAdr structure for initialization. 0xA0000000(Default).
+**/
+ UINT32 GmAdr;
+
+/** Offset 0x0044 - Enable PavpLock
+ Enable/disable PavpLock. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 PavpLock;
+
+/** Offset 0x0045 - Enable GraphicsFreqModify
+ Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 GraphicsFreqModify;
+
+/** Offset 0x0046 - Enable GraphicsFreqReq
+ Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 GraphicsFreqReq;
+
+/** Offset 0x0047 - Enable GraphicsVideoFreq
+ Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 GraphicsVideoFreq;
+
+/** Offset 0x0048 - Enable PmLock
+ Enable/disable PmLock. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 PmLock;
+
+/** Offset 0x0049 - Enable DopClockGating
+ Enable/disable DopClockGating. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 DopClockGating;
+
+/** Offset 0x004A - Enable UnsolicitedAttackOverride
+ Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 UnsolicitedAttackOverride;
+
+/** Offset 0x004B - Enable WOPCMSupport
+ Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 WOPCMSupport;
+
+/** Offset 0x004C - Enable WOPCMSize
+ Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 WOPCMSize;
+
+/** Offset 0x004D - Enable PowerGating
+ Enable/disable PowerGating. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 PowerGating;
+
+/** Offset 0x004E - Enable UnitLevelClockGating
+ Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 UnitLevelClockGating;
+
+/** Offset 0x004F - Enable FastBoot
+ Enable/disable FastBoot. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 FastBoot;
+
+/** Offset 0x0050 - Enable DynSR
+ Enable/disable DynSR. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 DynSR;
+
+/** Offset 0x0051 - Enable SaIpuEnable
+ Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 SaIpuEnableReserved;
+
+/** Offset 0x0052 - GT PM Support
+ Enable/Disable GT power management support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 PmSupport;
+
+/** Offset 0x0053 - RC6(Render Standby)
+ Enable/Disable render standby support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 EnableRenderStandby;
+
+/** Offset 0x0054 - BMP Logo Data Size
+ BMP logo data buffer size. 0x00000000(Default).
+**/
+ UINT32 LogoSize;
+
+/** Offset 0x0058 - BMP Logo Data Pointer
+ BMP logo data pointer to a BMP format buffer. 0x00000000(Default).
+**/
+ UINT32 LogoPtr;
+
+/** Offset 0x005C - Graphics Configuration Data Pointer
+ Graphics configuration data used for initialization. 0x00000000(Default).
+**/
+ UINT32 GraphicsConfigPtr;
+
+/** Offset 0x0060 - PAVP Enable
+ Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 PavpEnable;
+
+/** Offset 0x0061 - PAVP PR3
+ Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 PavpPr3;
+
+/** Offset 0x0062 - CdClock Frequency selection
+ 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default).
+ 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz
+**/
+ UINT8 CdClock;
+
+/** Offset 0x0063 - Enable/Disable PeiGraphicsPeimInit
+ Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 PeiGraphicsPeimInit;
+
+/** Offset 0x0064 - Write Protection Support
+ Enable/disable Write Protection. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 WriteProtectionEnable[5];
+
+/** Offset 0x0069 - Read Protection Support
+ Enable/disable Read Protection. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 ReadProtectionEnable[5];
+
+/** Offset 0x006E - Protected Range Limitation
+ The address of the upper limit of protection, 0x0FFFh(Default).
+**/
+ UINT16 ProtectedRangeLimit[5];
+
+/** Offset 0x0078 - Protected Range Base
+ The base address of the upper limit of protection. 0x0000(Default).
+**/
+ UINT16 ProtectedRangeBase[5];
+
+/** Offset 0x0082 - Enable SC Gaussian Mixture Models
+ Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 Gmm;
+
+/** Offset 0x0083 - GMM Clock Gating - PGCB Clock Trunk
+ Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 ClkGatingPgcbClkTrunk;
+
+/** Offset 0x0084 - GMM Clock Gating - Sideband
+ Enable/disable Sideband. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 ClkGatingSb;
+
+/** Offset 0x0085 - GMM Clock Gating - Sideband
+ Enable/disable Sideband. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 ClkGatingSbClkTrunk;
+
+/** Offset 0x0086 - GMM Clock Gating - Sideband Clock Partition
+ Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 ClkGatingSbClkPartition;
+
+/** Offset 0x0087 - GMM Clock Gating - Core
+ Enable/disable Core. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 ClkGatingCore;
+
+/** Offset 0x0088 - GMM Clock Gating - DMA
+ Enable/disable DMA. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 ClkGatingDma;
+
+/** Offset 0x0089 - GMM Clock Gating - Register Access
+ Enable/disable Register Access. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 ClkGatingRegAccess;
+
+/** Offset 0x008A - GMM Clock Gating - Host
+ Enable/disable Host. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 ClkGatingHost;
+
+/** Offset 0x008B - GMM Clock Gating - Partition
+ Enable/disable Partition. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 ClkGatingPartition;
+
+/** Offset 0x008C - Clock Gating - Trunk
+ Enable/disable Trunk. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 ClkGatingTrunk;
+
+/** Offset 0x008D - HD Audio Support
+ Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 HdaEnable;
+
+/** Offset 0x008E - HD Audio DSP Support
+ Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 DspEnable;
+
+/** Offset 0x008F - Azalia wake-on-ring
+ Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 Pme;
+
+/** Offset 0x0090 - HD-Audio I/O Buffer Ownership
+ Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default)
+ 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and
+ I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers
+**/
+ UINT8 HdAudioIoBufferOwnership;
+
+/** Offset 0x0091 - HD-Audio I/O Buffer Voltage
+ HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V.
+ 0: 3.3V, 1: 1.8V
+**/
+ UINT8 HdAudioIoBufferVoltage;
+
+/** Offset 0x0092 - HD-Audio Virtual Channel Type
+ HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1.
+ 0: VC0, 1: VC1
+**/
+ UINT8 HdAudioVcType;
+
+/** Offset 0x0093 - HD-Audio Link Frequency
+ HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,
+ 4:96MHz, 5:Invalid.
+ 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid
+**/
+ UINT8 HdAudioLinkFrequency;
+
+/** Offset 0x0094 - HD-Audio iDisp-Link Frequency
+ HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,
+ 4:96MHz, 5:Invalid.
+ 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid
+**/
+ UINT8 HdAudioIDispLinkFrequency;
+
+/** Offset 0x0095 - HD-Audio iDisp-Link T-Mode
+ HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T.
+ 0: 2T, 1: 1T
+**/
+ UINT8 HdAudioIDispLinkTmode;
+
+/** Offset 0x0096 - HD-Audio Disp DMIC
+ HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array.
+ 0: Disable, 1: 2ch array, 2: 4ch array
+**/
+ UINT8 DspEndpointDmic;
+
+/** Offset 0x0097 - HD-Audio Bluetooth
+ Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 DspEndpointBluetooth;
+
+/** Offset 0x0098 - HD-Audio I2S SHK
+ Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 DspEndpointI2sSkp;
+
+/** Offset 0x0099 - HD-Audio I2S HP
+ Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 DspEndpointI2sHp;
+
+/** Offset 0x009A - HD-Audio Controller Power Gating
+ Enable/Disable HD-Audio Controller Power Gating. This option is deprecated.
+ $EN_DIS
+**/
+ UINT8 AudioCtlPwrGate;
+
+/** Offset 0x009B - HD-Audio ADSP Power Gating
+ Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated.
+ $EN_DIS
+**/
+ UINT8 AudioDspPwrGate;
+
+/** Offset 0x009C - HD-Audio CSME Memory Transfers
+ Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2.
+ 0: VC0, 1: VC2
+**/
+ UINT8 Mmt;
+
+/** Offset 0x009D - HD-Audio Host Memory Transfers
+ Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2.
+ 0: VC0, 1: VC2
+**/
+ UINT8 Hmt;
+
+/** Offset 0x009E - HD-Audio Power Gating
+ Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 HDAudioPwrGate;
+
+/** Offset 0x009F - HD-Audio Clock Gatingn
+ Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 HDAudioClkGate;
+
+/** Offset 0x00A0 - Bitmask of DSP Feature
+ Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default).
+ [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6]
+ - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:
+ Intel WoV, 1: Windows Voice Activation
+**/
+ UINT32 DspFeatureMask;
+
+/** Offset 0x00A4 - Bitmask of supported DSP Post-Processing Modules
+ Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default).
+ [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6]
+ - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:
+ Intel WoV, 1: Windows Voice Activation
+**/
+ UINT32 DspPpModuleMask;
+
+/** Offset 0x00A8 - HD-Audio BIOS Configuration Lock Down
+ Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.
+ This option is deprecated
+ $EN_DIS
+**/
+ UINT8 BiosCfgLockDown;
+
+/** Offset 0x00A9 - Enable High Precision Timer
+ Enable/Disable Hpet. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 Hpet;
+
+/** Offset 0x00AA - Hpet Valid BDF Value
+ Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 HpetBdfValid;
+
+/** Offset 0x00AB - Bus Number of Hpet
+ Completer ID of Bus Number of Hpet. Default = 0xFA(Default).
+**/
+ UINT8 HpetBusNumber;
+
+/** Offset 0x00AC - Device Number of Hpet
+ Completer ID of Device Number of Hpet. 0x1F(Default).
+**/
+ UINT8 HpetDeviceNumber;
+
+/** Offset 0x00AD - Function Number of Hpet
+ Completer ID of Function Number of Hpet. 0x00(Default).
+**/
+ UINT8 HpetFunctionNumber;
+
+/** Offset 0x00AE - IoApic Valid BDF Value
+ Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 IoApicBdfValid;
+
+/** Offset 0x00AF - Bus Number of IoApic
+ Completer ID of Bus Number of IoApic. 0xFA(Default).
+**/
+ UINT8 IoApicBusNumber;
+
+/** Offset 0x00B0 - Device Number of IoApic
+ Completer ID of Device Number of IoApic. 0x0F(Default).
+**/
+ UINT8 IoApicDeviceNumber;
+
+/** Offset 0x00B1 - Function Number of IoApic
+ Completer ID of Function Number of IoApic. 0x00(Default).
+**/
+ UINT8 IoApicFunctionNumber;
+
+/** Offset 0x00B2 - IOAPIC Entry 24-119
+ Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 IoApicEntry24_119;
+
+/** Offset 0x00B3 - IO APIC ID
+ This member determines IOAPIC ID. 0x01(Default).
+**/
+ UINT8 IoApicId;
+
+/** Offset 0x00B4 - IoApic Range
+ Define address bits 19:12 for the IOxAPIC range. 0x00(Default).
+**/
+ UINT8 IoApicRangeSelect;
+
+/** Offset 0x00B5 - ISH Controller
+ Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 IshEnable;
+
+/** Offset 0x00B6 - BIOS Interface Lock Down
+ Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control
+ Register. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 BiosInterface;
+
+/** Offset 0x00B7 - Bios LockDown Enable
+ Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 BiosLock;
+
+/** Offset 0x00B8 - SPI EISS Status
+ Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 SpiEiss;
+
+/** Offset 0x00B9 - BiosLock SWSMI Number
+ This member describes the SwSmi value for Bios Lock. 0xA9(Default).
+**/
+ UINT8 BiosLockSwSmiNumber;
+
+/** Offset 0x00BA - LPSS IOSF PMCTL S0ix Enable
+ Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 LPSS_S0ixEnable;
+
+/** Offset 0x00BB
+**/
+ UINT8 UnusedUpdSpace0[1];
+
+/** Offset 0x00BC - LPSS I2C Clock Gating Configuration
+ Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 I2cClkGateCfg[8];
+
+/** Offset 0x00C4 - PSS HSUART Clock Gating Configuration
+ Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 HsuartClkGateCfg[4];
+
+/** Offset 0x00C8 - LPSS SPI Clock Gating Configuration
+ Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 SpiClkGateCfg[3];
+
+/** Offset 0x00CB - I2C Device 0
+ Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 I2c0Enable;
+
+/** Offset 0x00CC - I2C Device 1
+ Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 I2c1Enable;
+
+/** Offset 0x00CD - I2C Device 2
+ Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 I2c2Enable;
+
+/** Offset 0x00CE - I2C Device 3
+ Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 I2c3Enable;
+
+/** Offset 0x00CF - I2C Device 4
+ Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 I2c4Enable;
+
+/** Offset 0x00D0 - I2C Device 5
+ Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 I2c5Enable;
+
+/** Offset 0x00D1 - I2C Device 6
+ Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 I2c6Enable;
+
+/** Offset 0x00D2 - I2C Device 7
+ Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 I2c7Enable;
+
+/** Offset 0x00D3 - UART Device 0
+ Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 Hsuart0Enable;
+
+/** Offset 0x00D4 - UART Device 1
+ Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 Hsuart1Enable;
+
+/** Offset 0x00D5 - UART Device 2
+ Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 Hsuart2Enable;
+
+/** Offset 0x00D6 - UART Device 3
+ Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 Hsuart3Enable;
+
+/** Offset 0x00D7 - SPI UART Device 0
+ Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 Spi0Enable;
+
+/** Offset 0x00D8 - SPI UART Device 1
+ Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 Spi1Enable;
+
+/** Offset 0x00D9 - SPI UART Device 2
+ Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode
+**/
+ UINT8 Spi2Enable;
+
+/** Offset 0x00DA - OS Debug Feature
+ Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable.
+ $EN_DIS
+**/
+ UINT8 OsDbgEnable;
+
+/** Offset 0x00DB - DCI Feature
+ Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable.
+ $EN_DIS
+**/
+ UINT8 DciEn;
+
+/** Offset 0x00DC - UART Debug Base Address
+ UART Debug Base Address. 0x00000000(Default).
+**/
+ UINT32 Uart2KernelDebugBaseAddress;
+
+/** Offset 0x00E0 - Enable PCIE Clock Gating
+ Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default).
+ 0:Enable, 1:Disable
+**/
+ UINT8 PcieClockGatingDisabled;
+
+/** Offset 0x00E1 - Enable PCIE Root Port 8xh Decode
+ Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 PcieRootPort8xhDecode;
+
+/** Offset 0x00E2 - PCIE 8xh Decode Port Index
+ PCIE 8xh Decode Port Index. 0x00(Default).
+**/
+ UINT8 Pcie8xhDecodePortIndex;
+
+/** Offset 0x00E3 - Enable PCIE Root Port Peer Memory Write
+ Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 PcieRootPortPeerMemoryWriteEnable;
+
+/** Offset 0x00E4 - PCIE SWSMI Number
+ This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default).
+**/
+ UINT8 PcieAspmSwSmiNumber;
+
+/** Offset 0x00E5
+**/
+ UINT8 UnusedUpdSpace1[1];
+
+/** Offset 0x00E6 - PCI Express Root Port
+ Control the PCI Express Root Port . 0:Disable, 1:Enable(Default).
+**/
+ UINT8 PcieRootPortEn[6];
+
+/** Offset 0x00EC - Hide PCIE Root Port Configuration Space
+ Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 PcieRpHide[6];
+
+/** Offset 0x00F2 - PCIE Root Port Slot Implement
+ Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 PcieRpSlotImplemented[6];
+
+/** Offset 0x00F8 - Hot Plug
+ PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 PcieRpHotPlug[6];
+
+/** Offset 0x00FE - PCIE PM SCI
+ Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 PcieRpPmSci[6];
+
+/** Offset 0x0104 - PCIE Root Port Extended Sync
+ Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 PcieRpExtSync[6];
+
+/** Offset 0x010A - Transmitter Half Swing
+ Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 PcieRpTransmitterHalfSwing[6];
+
+/** Offset 0x0110 - ACS
+ Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 PcieRpAcsEnabled[6];
+
+/** Offset 0x0116 - Clock Request Support
+ Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 PcieRpClkReqSupported[6];
+
+/** Offset 0x011C - Configure CLKREQ Number
+ Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00,
+ 0x01, 0x02, 0x03.
+**/
+ UINT8 PcieRpClkReqNumber[6];
+
+/** Offset 0x0122 - CLKREQ# Detection
+ Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable.
+**/
+ UINT8 PcieRpClkReqDetect[6];
+
+/** Offset 0x0128 - Advanced Error Reporting
+ Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable.
+**/
+ UINT8 AdvancedErrorReporting[6];
+
+/** Offset 0x012E - PME Interrupt
+ Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable.
+**/
+ UINT8 PmeInterrupt[6];
+
+/** Offset 0x0134 - URR
+ PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 UnsupportedRequestReport[6];
+
+/** Offset 0x013A - FER
+ PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 FatalErrorReport[6];
+
+/** Offset 0x0140 - NFER
+ PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 NoFatalErrorReport[6];
+
+/** Offset 0x0146 - CER
+ PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 CorrectableErrorReport[6];
+
+/** Offset 0x014C - SEFE
+ Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 SystemErrorOnFatalError[6];
+
+/** Offset 0x0152 - SENFE
+ Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 SystemErrorOnNonFatalError[6];
+
+/** Offset 0x0158 - SECE
+ Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 SystemErrorOnCorrectableError[6];
+
+/** Offset 0x015E - PCIe Speed
+ Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3.
+**/
+ UINT8 PcieRpSpeed[6];
+
+/** Offset 0x0164 - Physical Slot Number
+ Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05.
+**/
+ UINT8 PhysicalSlotNumber[6];
+
+/** Offset 0x016A - CTO
+ Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable.
+**/
+ UINT8 PcieRpCompletionTimeout[6];
+
+/** Offset 0x0170 - PTM Support
+ Enable/Disable PTM Support. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 PtmEnable[6];
+
+/** Offset 0x0176 - ASPM
+ PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1,
+ 4:Auto(Default).
+**/
+ UINT8 PcieRpAspm[6];
+
+/** Offset 0x017C - L1 Substates
+ PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default).
+**/
+ UINT8 PcieRpL1Substates[6];
+
+/** Offset 0x0182 - PCH PCIe LTR
+ PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 PcieRpLtrEnable[6];
+
+/** Offset 0x0188 - PCIE LTR Lock
+ PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 PcieRpLtrConfigLock[6];
+
+/** Offset 0x018E - PME_B0_S5 Disable bit
+ PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 PmeB0S5Dis;
+
+/** Offset 0x018F - PCI Clock Run
+ This member describes whether or not the PCI ClockRun feature of SC should be enabled.
+ 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 PciClockRun;
+
+/** Offset 0x0190 - Enable/Disable Timer 8254 Clock Setting
+ Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 Timer8254ClkSetting;
+
+/** Offset 0x0191 - Chipset SATA
+ Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports
+ the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 EnableSata;
+
+/** Offset 0x0192 - SATA Mode Selection
+ Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID.
+ 0:AHCI, 1:RAID
+**/
+ UINT8 SataMode;
+
+/** Offset 0x0193 - Aggressive LPM Support
+ Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 SataSalpSupport;
+
+/** Offset 0x0194 - SATA Power Optimization
+ Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 SataPwrOptEnable;
+
+/** Offset 0x0195 - eSATA Speed Limit
+ Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 eSATASpeedLimit;
+
+/** Offset 0x0196 - SATA Speed Limit
+ SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3).
+ 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1)
+**/
+ UINT8 SpeedLimit;
+
+/** Offset 0x0197
+**/
+ UINT8 UnusedUpdSpace2[1];
+
+/** Offset 0x0198 - SATA Port
+ Enable or Disable SATA Port. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 SataPortsEnable[2];
+
+/** Offset 0x019A - SATA Port DevSlp
+ Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 SataPortsDevSlp[2];
+
+/** Offset 0x019C - SATA Port HotPlug
+ Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable.
+**/
+ UINT8 SataPortsHotPlug[2];
+
+/** Offset 0x019E - Mechanical Presence Switch
+ Controls reporting if this port has an Mechanical Presence Switch.\n
+ Note:Requires hardware support. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 SataPortsInterlockSw[2];
+
+/** Offset 0x01A0 - External SATA Ports
+ Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 SataPortsExternal[2];
+
+/** Offset 0x01A2 - Spin Up Device
+ Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 SataPortsSpinUp[2];
+
+/** Offset 0x01A4 - SATA Solid State
+ Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard
+ Disk Drive(Default), 1:Solid State Drive.
+**/
+ UINT8 SataPortsSolidStateDrive[2];
+
+/** Offset 0x01A6 - DITO Configuration
+ Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable.
+**/
+ UINT8 SataPortsEnableDitoConfig[2];
+
+/** Offset 0x01A8 - DM Value
+ DM Value. 0:Minimum, 0x0F:Maximum(Default).
+**/
+ UINT8 SataPortsDmVal[2];
+
+/** Offset 0x01AA
+**/
+ UINT8 UnusedUpdSpace3[2];
+
+/** Offset 0x01AC - DITO Value
+ DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default).
+**/
+ UINT16 SataPortsDitoVal[2];
+
+/** Offset 0x01B0 - Subsystem Vendor ID
+ Subsystem Vendor ID. 0x8086(Default).
+**/
+ UINT16 SubSystemVendorId;
+
+/** Offset 0x01B2 - Subsystem ID
+ Subsystem ID. 0x7270(Default).
+**/
+ UINT16 SubSystemId;
+
+/** Offset 0x01B4 - CRIDSettings
+ PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3.
+**/
+ UINT8 CRIDSettings;
+
+/** Offset 0x01B5 - ResetSelect
+ ResetSelect. 0x6:warm reset(Default), 0xE:cold reset.
+**/
+ UINT8 ResetSelect;
+
+/** Offset 0x01B6 - SD Card Support (D27:F0)
+ Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 SdcardEnabled;
+
+/** Offset 0x01B7 - SeMMC Support (D28:F0)
+ Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 eMMCEnabled;
+
+/** Offset 0x01B8 - eMMC Max Speed
+ Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50.
+ 0:HS400, 1: HS200, 2:DDR50
+**/
+ UINT8 eMMCHostMaxSpeed;
+
+/** Offset 0x01B9 - UFS Support (D29:F0)
+ Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 UfsEnabled;
+
+/** Offset 0x01BA - SDIO Support (D30:F0)
+ Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 SdioEnabled;
+
+/** Offset 0x01BB - GPP Lock Feature
+ Enable/Disable GPP lock. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 GppLock;
+
+/** Offset 0x01BC - Serial IRQ
+ Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 SirqEnable;
+
+/** Offset 0x01BD - Serial IRQ Mode
+ Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode.
+ $EN_DIS
+**/
+ UINT8 SirqMode;
+
+/** Offset 0x01BE - Start Frame Pulse Width
+ Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk.
+ 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk
+**/
+ UINT8 StartFramePulse;
+
+/** Offset 0x01BF - Enable SMBus
+ Enable/disable SMBus controller. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 SmbusEnable;
+
+/** Offset 0x01C0 - SMBus ARP Support
+ Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 ArpEnable;
+
+/** Offset 0x01C1
+**/
+ UINT8 UnusedUpdSpace4;
+
+/** Offset 0x01C2 - SMBus Table Elements
+ The number of elements in the Reserved SMBus Address Table. 0x0080(Default).
+**/
+ UINT16 NumRsvdSmbusAddresses;
+
+/** Offset 0x01C4 - Reserved SMBus Address Table
+ Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default).
+**/
+ UINT8 RsvdSmbusAddressTable[128];
+
+/** Offset 0x0244 - XHCI Disable Compliance Mode
+ Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance
+ Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True.
+ $EN_DIS
+**/
+ UINT8 DisableComplianceMode;
+
+/** Offset 0x0245 - USB Per-Port Control
+ Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 UsbPerPortCtl;
+
+/** Offset 0x0246 - xHCI Mode
+ Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default)
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 Usb30Mode;
+
+/** Offset 0x0247
+**/
+ UINT8 UnusedUpdSpace5[1];
+
+/** Offset 0x0248 - Enable USB2 ports
+ Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on. 0x01(Default).
+**/
+ UINT8 PortUsb20Enable[8];
+
+/** Offset 0x0250 - USB20 Over Current Pin
+ Over Current Pin number of USB 2.0 Port. 0x00(Default).
+**/
+ UINT8 PortUs20bOverCurrentPin[8];
+
+/** Offset 0x0258 - XDCI Support
+ Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode.
+ 0:Disable, 1:PCI_Mode, 2:ACPI_mode
+**/
+ UINT8 UsbOtg;
+
+/** Offset 0x0259 - Enable XHCI HSIC Support
+ Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 HsicSupportEnable;
+
+/** Offset 0x025A - Enable USB3 ports
+ Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on. 0x01(Default).
+**/
+ UINT8 PortUsb30Enable[6];
+
+/** Offset 0x0260 - USB20 Over Current Pin
+ Over Current Pin number of USB 3.0 Port. 0x01(Default).
+**/
+ UINT8 PortUs30bOverCurrentPin[6];
+
+/** Offset 0x0266 - Enable XHCI SSIC Support
+ Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for
+ port1. 0x00(Default).
+**/
+ UINT8 SsicPortEnable[2];
+
+/** Offset 0x0268 - SSIC Dlane PowerGating
+ Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT16 DlanePwrGating;
+
+/** Offset 0x026A - VT-d
+ Enable/Disable VT-d. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 VtdEnable;
+
+/** Offset 0x026B - SMI Lock bit
+ Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable,
+ 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 LockDownGlobalSmi;
+
+/** Offset 0x026C - HDAudio Delay Timer
+ The delay timer after Azalia reset. 0x012C(Default).
+**/
+ UINT16 ResetWaitTimer;
+
+/** Offset 0x026E - RTC Lock Bits
+ Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 RtcLock;
+
+/** Offset 0x026F - SATA Test Mode Selection
+ Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 SataTestMode;
+
+/** Offset 0x0270 - XHCI SSIC RATE
+ Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series.
+**/
+ UINT8 SsicRate[2];
+
+/** Offset 0x0272 - SMBus Dynamic Power Gating
+ Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT16 DynamicPowerGating;
+
+/** Offset 0x0274 - Max Snoop Latency
+ Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default).
+**/
+ UINT16 PcieRpLtrMaxSnoopLatency[6];
+
+/** Offset 0x0280 - Snoop Latency Override
+ Snoop Latency Override for PCH PCIE. \n
+ Disabled:Disable override.\n
+ Manual:Manually enter override values.\n
+ Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).
+**/
+ UINT8 PcieRpSnoopLatencyOverrideMode[6];
+
+/** Offset 0x0286
+**/
+ UINT8 UnusedUpdSpace6[2];
+
+/** Offset 0x0288 - Snoop Latency Value
+ LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).
+**/
+ UINT16 PcieRpSnoopLatencyOverrideValue[6];
+
+/** Offset 0x0294 - Snoop Latency Multiplier
+ LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns,
+ 4:1048576ns, 5:33554432ns.
+**/
+ UINT8 PcieRpSnoopLatencyOverrideMultiplier[6];
+
+/** Offset 0x029A - Skip Multi-Processor Initialization
+ When this is skipped, boot loader must initialize processors before SilicionInit
+ API. 0: Initialize(Default), <b>1: Skip
+ $EN_DIS
+**/
+ UINT8 SkipMpInit;
+
+/** Offset 0x029B - DCI Auto Detect
+ Enable/disable DCI AUTO mode. Enabled(Default).
+ $EN_DIS
+**/
+ UINT8 DciAutoDetect;
+
+/** Offset 0x029C - Max Non-Snoop Latency
+ Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default).
+**/
+ UINT16 PcieRpLtrMaxNonSnoopLatency[6];
+
+/** Offset 0x02A8 - Non Snoop Latency Override
+ Non Snoop Latency Override for PCH PCIE. \n
+ Disabled:Disable override.\n
+ Manual:Manually enter override values.\n
+ Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).
+**/
+ UINT8 PcieRpNonSnoopLatencyOverrideMode[6];
+
+/** Offset 0x02AE - Halt and Lock TCO Timer
+ Halt and Lock the TCO Timer (Watchdog).
+ 0:No, 1:Yes (default)
+**/
+ UINT8 TcoTimerHaltLock;
+
+/** Offset 0x02AF - Power Button Override Period
+ specifies how long will PMC wait before initiating a global reset. 000b-4s(default),
+ 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.)
+ 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s
+**/
+ UINT8 PwrBtnOverridePeriod;
+
+/** Offset 0x02B0 - Non Snoop Latency Value
+ LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).
+**/
+ UINT16 PcieRpNonSnoopLatencyOverrideValue[6];
+
+/** Offset 0x02BC - Non Snoop Latency Multiplier
+ LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default),
+ 3:32768ns, 4:1048576ns, 5:33554432ns.
+**/
+ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[6];
+
+/** Offset 0x02C2 - PCIE Root Port Slot Power Limit Scale
+ Specifies scale used for slot power limit value. 0x00(Default).
+**/
+ UINT8 PcieRpSlotPowerLimitScale[6];
+
+/** Offset 0x02C8 - PCIE Root Port Slot Power Limit Value
+ Specifies upper limit on power supplie by slot. 0x00(Default).
+**/
+ UINT8 PcieRpSlotPowerLimitValue[6];
+
+/** Offset 0x02CE - Power Button Native Mode Disable
+ Disable power button native mode, when 1, this will result in the PMC logic constantly
+ seeing the power button as de-asserted. 0 (default))
+ $EN_DIS
+**/
+ UINT8 DisableNativePowerButton;
+
+/** Offset 0x02CF - Power Button Debounce Mode
+ Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default)
+ $EN_DIS
+**/
+ UINT8 PowerButterDebounceMode;
+
+/** Offset 0x02D0 - SDIO_TX_CMD_DLL_CNTL
+ SDIO_TX_CMD_DLL_CNTL. 0x505(Default).
+**/
+ UINT32 SdioTxCmdCntl;
+
+/** Offset 0x02D4 - SDIO_TX_DATA_DLL_CNTL1
+ SDIO_TX_DATA_DLL_CNTL1. 0xE(Default).
+**/
+ UINT32 SdioTxDataCntl1;
+
+/** Offset 0x02D8 - SDIO_TX_DATA_DLL_CNTL2
+ SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default).
+**/
+ UINT32 SdioTxDataCntl2;
+
+/** Offset 0x02DC - SDIO_RX_CMD_DATA_DLL_CNTL1
+ SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default).
+**/
+ UINT32 SdioRxCmdDataCntl1;
+
+/** Offset 0x02E0 - SDIO_RX_CMD_DATA_DLL_CNTL2
+ SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).
+**/
+ UINT32 SdioRxCmdDataCntl2;
+
+/** Offset 0x02E4 - SDCARD_TX_CMD_DLL_CNTL
+ SDCARD_TX_CMD_DLL_CNTL. 0x505(Default).
+**/
+ UINT32 SdcardTxCmdCntl;
+
+/** Offset 0x02E8 - SDCARD_TX_DATA_DLL_CNTL1
+ SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default).
+**/
+ UINT32 SdcardTxDataCntl1;
+
+/** Offset 0x02EC - SDCARD_TX_DATA_DLL_CNTL2
+ SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default).
+**/
+ UINT32 SdcardTxDataCntl2;
+
+/** Offset 0x02F0 - SDCARD_RX_CMD_DATA_DLL_CNTL1
+ SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default).
+**/
+ UINT32 SdcardRxCmdDataCntl1;
+
+/** Offset 0x02F4 - SDCARD_RX_STROBE_DLL_CNTL
+ SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default).
+**/
+ UINT32 SdcardRxStrobeCntl;
+
+/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL2
+ SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).
+**/
+ UINT32 SdcardRxCmdDataCntl2;
+
+/** Offset 0x02FC - EMMC_TX_CMD_DLL_CNTL
+ EMMC_TX_CMD_DLL_CNTL. 0x505(Default).
+**/
+ UINT32 EmmcTxCmdCntl;
+
+/** Offset 0x0300 - EMMC_TX_DATA_DLL_CNTL1
+ EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default).
+**/
+ UINT32 EmmcTxDataCntl1;
+
+/** Offset 0x0304 - EMMC_TX_DATA_DLL_CNTL2
+ EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default).
+**/
+ UINT32 EmmcTxDataCntl2;
+
+/** Offset 0x0308 - EMMC_RX_CMD_DATA_DLL_CNTL1
+ EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default).
+**/
+ UINT32 EmmcRxCmdDataCntl1;
+
+/** Offset 0x030C - EMMC_RX_STROBE_DLL_CNTL
+ EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default).
+**/
+ UINT32 EmmcRxStrobeCntl;
+
+/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL2
+ EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default).
+**/
+ UINT32 EmmcRxCmdDataCntl2;
+
+/** Offset 0x0314 - EMMC_MASTER_DLL_CNTL
+ EMMC_MASTER_DLL_CNTL. 0x001(Default).
+**/
+ UINT32 EmmcMasterSwCntl;
+
+/** Offset 0x0318 - SGX Epoch 0
+ SGX Epoch 0. 0x0(Default).
+**/
+ UINT64 SgxEpoch0;
+
+/** Offset 0x0320 - SGX Epoch 1
+ SGX Epoch 1. 0x0(Default).
+**/
+ UINT64 SgxEpoch1;
+
+/** Offset 0x0328 - MicrocodePatchAddress
+ MicrocodePatchAddress. 0x0(Default).
+**/
+ UINT64 MicrocodePatchAddress;
+
+/** Offset 0x0330 - PCIe Selectable De-emphasis
+ When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis
+ for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default).
+**/
+ UINT8 PcieRpSelectableDeemphasis[6];
+
+/** Offset 0x0336 - Monitor Mwait Enable
+ Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux
+ based OS, this should be Disabled. 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 MonitorMwaitEnable;
+
+/** Offset 0x0337 - Universal Audio Architecture compliance for DSP enabled system
+ 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
+ driver or SST driver supported).
+ $EN_DIS
+**/
+ UINT8 HdAudioDspUaaCompliance;
+
+/** Offset 0x0338 - IRQ Interrupt Polarity Control
+ Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low
+**/
+ UINT32 IPC[4];
+
+/** Offset 0x0348 - Disable ModPHY dynamic power gate
+ Disable ModPHY dynamic power gate for the specific SATA port.
+**/
+ UINT8 SataPortsDisableDynamicPg[2];
+
+/** Offset 0x034A - Init CPU during S3 resume
+ 0: Do not initialize CPU during S3 resume. 1: Initialize CPU during S3 resume.
+ $EN_DIS
+**/
+ UINT8 InitS3Cpu;
+
+/** Offset 0x034B - CNVi Mode
+ Selects CNVi Mode. 0:Disable, 1:Auto(Default).
+ $EN_DIS
+**/
+ UINT8 CnviMode;
+
+/** Offset 0x034C - BT Interface
+ CNVi BT interface. 0:UART, 1:USB(Default).
+ $EN_DIS
+**/
+ UINT8 CnviBtInterface;
+
+/** Offset 0x034D - Disable Sx Wake
+ Enables/Disables wake from Sx . 0:No(Default), 1:Yes.
+ $EN_DIS
+**/
+ UINT8 DisableSxWake;
+
+/** Offset 0x034E - ModifyCrfGpios
+ Feature to Configure CRF Gpios Conditionally upon platform requirement, configuration
+ of GNSS and BtOnUart gpios will/will not be done based on this policy
+ $EN_DIS
+**/
+ UINT8 ModifyCrfGpios;
+
+/** Offset 0x034F - dGPU Hold Reset
+ dGPU Hold Reset GPIO information from GPIO community, Pin and Active
+**/
+ UINT8 HgDgpuHoldRst[8];
+
+/** Offset 0x0357 - dGPU Power Enable
+ dGPU power enable GPIO information from GPIO community, Pin and Active
+**/
+ UINT8 HgDgpuPwrEnable[8];
+
+/** Offset 0x035F - HG Enable
+ Enables/Disables Hybrid Graphics . 0 : Disable(Default), 1 : Enable
+ 0x1:Enabled, 0x0:Disabled
+**/
+ UINT8 HgEnabled;
+
+/** Offset 0x0360 - dGPU Delay after power enable
+ Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum ,
+ 300 : Default
+ 0 : Minimum , 1000 : Maximum , 300 : Default
+**/
+ UINT16 HgDelayAfterPwrEn;
+
+/** Offset 0x0362 - dGPU Delay after hold reset
+ Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum ,
+ 100 : Default
+ 0 : Minimum , 1000 : Maximum , 100 : Default
+**/
+ UINT16 HgDelayAfterHoldReset;
+
+/** Offset 0x0364 - CpuS3ResumeMtrrDataSize
+ Size of S3 resume MTRR data.
+**/
+ UINT16 CpuS3ResumeMtrrDataSize;
+
+/** Offset 0x0366 - PAVP ASMF
+ Enable/Disable PAVP ASMF 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 PavpAsmf;
+
+/** Offset 0x0367 - PAVP Auto TearDown Grace Period Enable
+ Enable/Disable PAVP Auto TearDown Grace Period 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 AutoTearDownGracePeriod;
+
+/** Offset 0x0368 - CpuS3ResumeMtrrData
+ Pointer CPU S3 Resume MTRR Data
+**/
+ UINT32 CpuS3ResumeMtrrData;
+
+/** Offset 0x036C - SeC EndOfPost EnableDisable
+ Enable/Disable SeC EOPEnable 0:Disable, 1:Enable(Default).
+ $EN_DIS
+**/
+ UINT8 EndOfPostEnabled;
+
+/** Offset 0x036D - EnableDigitalThermalSensor EnableDisable
+ Enable/Disable EnableDigitalThermalSensor 0:Disable(Default), 1:Enable.
+ $EN_DIS
+**/
+ UINT8 EnableDigitalThermalSensor;
+
+/** Offset 0x036E - PNP Mode
+ Select PNP Mode. 0:Disable,1:Power,2:Performance,3:Power&Performance
+ 0:Disable,1:Power,2:Performance,3:Power&Performance(default)
+**/
+ UINT8 PnpSettings;
+
+/** Offset 0x036F - OsBoot EnableDisable
+ Select OsBoot. 1:EMMC boot, 0:HardDisk boot
+ 1:EMMC boot, 1:HardDisk boot
+**/
+ UINT8 OsBoot;
+
+/** Offset 0x0370 - System Vendor ID
+ Upd for vendor ID for assigning to devices
+**/
+ UINT16 SiSVID;
+
+/** Offset 0x0372 - Sub system Vendor ID
+ Upd for subsystem ID for assigning to devices
+**/
+ UINT16 SiSSID;
+
+/** Offset 0x0374 - CpuBistData
+ Pointer CPU BIST Data
+**/
+ UINT32 CpuBistData;
+
+/** Offset 0x0378 - Base of memory region allocated for Processor Trace
+ Base address of memory region allocated for Processor Trace. Processor Trace requires
+ 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
+**/
+ UINT64 ProcessorTraceMemBase;
+
+/** Offset 0x0380 - Memory region allocation for Processor Trace
+ Length in bytes of memory region allocated for Processor Trace. Processor Trace
+ requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
+**/
+ UINT32 ProcessorTraceMemLength;
+
+/** Offset 0x0384 - AP threads Idle Manner
+ AP threads Idle Manner for waiting signal to run 1:HALT loop 2:MWAIT loop 3:RUN lOOP
+ $EN_DIS
+**/
+ UINT8 ApIdleManner;
+
+/** Offset 0x0385 - Skip P-unit Initialization
+ When this is skipped, boot loader must initialize P-unit before SilicionInit API.
+ 0: Initialize(Default), 1: Skip
+ $EN_DIS
+**/
+ UINT8 SkipPunitInit;
+
+/** Offset 0x0386 - Sub system Vendor ID VGA
+ Graphics PCI subsystem HgSubSystemId
+**/
+ UINT16 HgSubSystemId;
+
+/** Offset 0x0388 - USB Per Port HS Preemphasis Bias
+ USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-40.5mV, 010b-60.5mV, 011b-102mV,
+ 100b-102mV, 101b-142mV, 110b-162.5mV, 111b-202.5mV. One byte for each port.
+**/
+ UINT8 Usb2AfePetxiset[8];
+
+/** Offset 0x0390 - USB Per Port HS Transmitter Bias
+ USB Per Port HS Transmitter Bias. 000b-0mV, 001b-40.5mV, 010b-60.5mV, 011b-102mV,
+ 100b-102mV, 101b-142mV, 110b-162.5mV, 111b-202.5mV. One byte for each port.
+**/
+ UINT8 Usb2AfeTxiset[8];
+
+/** Offset 0x0398 - USB Per Port HS Transmitter Emphasis
+ USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
+ 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
+**/
+ UINT8 Usb2AfePredeemp[8];
+
+/** Offset 0x03A0 - USB Per Port Half Bit Pre-emphasis
+ USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
+ One byte for each port.
+**/
+ UINT8 Usb2AfePehalfbit[8];
+
+/** Offset 0x03A8 - Intel Processor Trace output Scheme method
+ Intel Processor Trace output Scheme method 0:Single Range Output (Default) 1. ToPA Output
+**/
+ UINT8 ProcessorTraceOutputScheme;
+
+/** Offset 0x03A9 - USB PDO Programming
+ Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
+ during later phase. 1: enable, 0: disable
+ 1: enable, 0: disable
+**/
+ UINT8 UsbPdoProgramming;
+
+/** Offset 0x03AA - Skip LPSS SPI Private Clock Parameter Programming
+ When this is skipped, boot loader must program LPSS SPI PCP. 0: Initialize(Default),
+ <b>1: Skip
+ $EN_DIS
+**/
+ UINT8 SkipSpiPCP;
+
+/** Offset 0x03AB - PMIC PCH_WROK delay configuration - IPC Configuration
+ Upd for changing PCH_WROK delay configuration : I2C_Slave_Address (31:23) + Register_Offset
+ (23:16) + OR Value (15:8) + AND Value (7:0)
+**/
+ UINT32 PmicPmcIpcCtrl;
+
+/** Offset 0x03AF - ModPhyIfValue
+ Upd To modify the Integrated Filter (IF) value as 0x12(Default) for WIN and 0x16
+ for Chrome
+**/
+ UINT8 ModPhyIfValue;
+
+/** Offset 0x03B0 - ModPhyVoltageBump
+ ModPhyVoltageBump. 1: enable, 0: disable
+ $EN_DIS
+**/
+ UINT8 ModPhyVoltageBump;
+
+/** Offset 0x03B1 - Vdd2 Voltage configuration
+ Upd for changing Vdd2 Voltage configuration : I2C_Slave_Address (31:23) + Register_Offset
+ (23:16) + OR Value (15:8) + AND Value (7:0)
+**/
+ UINT32 PmicVdd2Voltage;
+
+/** Offset 0x03B5
+**/
+ UINT8 ReservedFspsUpd[1];
+} FSP_S_CONFIG;
+
+/** Fsp S SGX Configuration
+**/
+typedef struct {
+
+/** Offset 0x03C0
+**/
+ UINT32 Signature;
+
+/** Offset 0x03C4 - Selective enable SGX
+ Selective enable SGX. 0xFFFF(Default).
+**/
+ UINT16 SelectiveEnableSgx;
+
+/** Offset 0x03C6 - SGX debug mode
+ Select SGX mode. 0:Disable(default), 1:Enable
+ 0:Disable(default), 1:Enable
+**/
+ UINT8 SgxDebugMode;
+
+/** Offset 0x03C7 - SGX Launch Control Policy Mode
+ Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default)
+ 0:Intel locked , 1:Unlocked mode(default) , 2: Locked mode
+**/
+ UINT8 SgxLcp;
+
+/** Offset 0x03C8 - LE KeyHash0
+ LE KeyHash0. 0x0(Default).
+**/
+ UINT64 SgxLePubKeyHash0;
+
+/** Offset 0x03D0 - LE KeyHash1
+ LE KeyHash1. 0x0(Default).
+**/
+ UINT64 SgxLePubKeyHash1;
+
+/** Offset 0x03D8 - LE KeyHash2
+ LE KeyHash2. 0x0(Default).
+**/
+ UINT64 SgxLePubKeyHash2;
+
+/** Offset 0x03E0
+**/
+ UINT8 UnusedUpdSpace8[16];
+
+/** Offset 0x03F0 - LE KeyHash3
+ LE KeyHash3. 0x0(Default).
+**/
+ UINT64 SgxLePubKeyHash3;
+
+/** Offset 0x03F8
+**/
+ UINT8 ReservedFspsSgxUpd[8];
+} FSP_S_SGX_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSP_S_CONFIG FspsConfig;
+
+/** Offset 0x03B6
+**/
+ UINT8 UnusedUpdSpace7[10];
+
+/** Offset 0x03C0
+**/
+ FSP_S_SGX_CONFIG FspsSgxConfig;
+
+/** Offset 0x0400
+**/
+ UINT8 UnusedUpdSpace9[6];
+
+/** Offset 0x0406
+**/
+ UINT16 UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 06:07:28 +0000