diff options
| author | Martin Roth <martinroth@chromium.org> | 2021-08-31 17:56:38 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-16 22:48:35 +0000 |
| commit | 40d2c04937480f4291bbe7d745a921c4f4e2c8e7 (patch) | |
| tree | a0fc74db52da5e241e5ec40ec590f326a4191d96 /src | |
| parent | 049e994fa81d9eaf2b3a41a04255c9d7b0ad596f (diff) | |
mb/google/guybrush: Reorganize bootblock_mainboard_early_init()
This now skips all of the pieces done by PSP_verstage.
BUG=None
TEST=Boot Guybrush with & without PSP_verstage
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5a6b8e2284e232c30c9f36ea7c6ab044e2644f7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/guybrush/bootblock.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index dc5e04657b..cd27632498 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -31,21 +31,6 @@ void bootblock_mainboard_early_init(void) size_t base_num_gpios, override_num_gpios; const struct soc_amd_gpio *base_gpios, *override_gpios; - if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { - base_gpios = variant_early_gpio_table(&base_num_gpios); - override_gpios = variant_early_override_gpio_table(&override_num_gpios); - - gpio_configure_pads_with_override(base_gpios, base_num_gpios, - override_gpios, override_num_gpios); - - /* Set a timer to make sure there's enough delay for - * the Fibocom 350 PCIe init - */ - stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US); - } - - printk(BIOS_DEBUG, "Bootblock configure eSPI\n"); - dword = pci_read_config32(SOC_LPC_DEV, 0x78); dword &= 0xFFFFF9F3; dword |= 0x200; @@ -53,6 +38,21 @@ void bootblock_mainboard_early_init(void) pci_write_config32(SOC_LPC_DEV, 0x44, 0); pci_write_config32(SOC_LPC_DEV, 0x48, 0); + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + base_gpios = variant_early_gpio_table(&base_num_gpios); + override_gpios = variant_early_override_gpio_table(&override_num_gpios); + + gpio_configure_pads_with_override(base_gpios, base_num_gpios, + override_gpios, override_num_gpios); + + /* Set a timer to make sure there's enough delay for + * the Fibocom 350 PCIe init + */ + stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US); + printk(BIOS_DEBUG, "Bootblock configure eSPI\n"); + dword = pm_read32(0x90); dword |= 1 << 16; pm_write32(0x90, dword); |