Drop prototype guarding for romcc

Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1]
made romcc not choke on function prototypes anymore. This
allows us to get rid of a lot of ifdefs guarding __ROMCC__ .

[1] http://review.coreboot.org/2424

Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3216
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

41 files changed, 31 insertions, 92 deletions

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index a3555d81d3..890c77f4f1 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -140,7 +140,6 @@ static inline unsigned int cpuid_edx(unsigned int op)
 #define X86_VENDOR_SIS       10
 #define X86_VENDOR_UNKNOWN 0xff
 
-#if !defined(__ROMCC__)
 #if !defined(__PRE_RAM__) && !defined(__SMM__)
 #include <device/device.h>
 
@@ -158,11 +157,7 @@ struct cpu_driver {
 	struct acpi_cstate *cstates;
 };
 
-struct device;
 struct cpu_driver *find_cpu_driver(struct device *cpu);
-#else
-#include <arch/io.h>
-#endif
 
 struct cpu_info {
 	device_t cpu;
@@ -187,7 +182,11 @@ static inline unsigned long cpu_index(void)
 	ci = cpu_info();
 	return ci->index;
 }
+#else
+#include <arch/io.h>
+#endif
 
+#ifndef __ROMCC__ // romcc is segfaulting in some cases
 struct cpuinfo_x86 {
         uint8_t    x86;            /* CPU family */
         uint8_t    x86_vendor;     /* CPU vendor */
@@ -195,7 +194,7 @@ struct cpuinfo_x86 {
         uint8_t    x86_mask;
 };
 
-static void inline get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
+static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
 {
         c->x86 = (tfms >> 8) & 0xf;
         c->x86_model = (tfms >> 4) & 0xf;
@@ -206,9 +205,8 @@ static void inline get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
                 c->x86_model += ((tfms >> 16) & 0xF) << 4;
 
 }
+#endif
 
 #define asmlinkage __attribute__((regparm(0)))
 
-#endif
-
 #endif /* ARCH_CPU_H */
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 8f4368fffc..c550cfa1a6 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -122,7 +122,7 @@
 # error "CONFIG_IED_REGION_SIZE is not a power of 2"
 #endif
 
-#ifndef __ROMCC__
+#if !defined(__ROMCC__) // FIXME romcc should handle below constructs
 
 #if defined(__PRE_RAM__)
 struct pei_data;
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index d440c7035f..1773cc88dc 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -97,7 +97,6 @@
 #define PSS_LATENCY_TRANSITION		10
 #define PSS_LATENCY_BUSMASTER		10
 
-#ifndef __ROMCC__
 #ifdef __SMM__
 /* Lock MSRs */
 void intel_model_206ax_finalize_smm(void);
@@ -106,6 +105,5 @@ void intel_model_206ax_finalize_smm(void);
 void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
 #endif
-#endif
 
 #endif
diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h
index 630252bd21..62424f14fd 100644
--- a/src/include/console/ne2k.h
+++ b/src/include/console/ne2k.h
@@ -1,5 +1,3 @@
-#ifndef _NE2K_H__
-#define _NE2K_H__
 /*
  * This file is part of the coreboot project.
  *
@@ -19,9 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef __ROMCC__
+#ifndef _NE2K_H__
+#define _NE2K_H__
 void ne2k_append_data(unsigned char *d, int len, unsigned int base);
 int ne2k_init(unsigned int eth_nic_base);
 void ne2k_transmit(unsigned int eth_nic_base);
-#endif
 #endif /* _NE2K_H */
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index c0467beccb..ee55c2f85e 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -511,7 +511,7 @@
 #define PMLogic_BASE		(0x9D00)
 
 
-#if !defined(__ROMCC__)  && !defined(__ASSEMBLER__)
+#if !defined(__ASSEMBLER__)
 #if defined(__PRE_RAM__)
 void cpuRegInit(void);
 void SystemPreInit(void);
diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h
index 632bfe2217..4eee1568fb 100644
--- a/src/include/cpu/amd/lxdef.h
+++ b/src/include/cpu/amd/lxdef.h
@@ -630,7 +630,7 @@
 #define DELAY_UPPER_DISABLE_CLK135	(1 << 23)
 #define DELAY_LOWER_STATUS_MASK		0x7C0
 
-#if !defined(__ROMCC__)  && !defined(__ASSEMBLER__)
+#if !defined(__ASSEMBLER__)
 #if defined(__PRE_RAM__)
 void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated);
 void SystemPreInit(void);
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index f4c4d7283b..8bfae60c1f 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -105,9 +105,7 @@ typedef struct {
 	int num_states;
 } sst_table_t;
 
-#ifndef __ROMCC__
 void speedstep_gen_pstates(sst_table_t *);
-#endif
 
 #define SPEEDSTEP_MAX_POWER_YONAH	31000
 #define SPEEDSTEP_MIN_POWER_YONAH	13100
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 54b2f5488f..d4f323208b 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -51,7 +51,6 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
 	return lapic_read(LAPIC_ID) >> 24;
 }
 
-#ifndef __ROMCC__
 #if !CONFIG_AP_IN_SIPI_WAIT
 /* If we need to go back to sipi wait, we use the long non-inlined version of
  * this function in lapic_cpu_init.c
@@ -155,6 +154,5 @@ int start_cpu(struct device *cpu);
 #endif /* !__PRE_RAM__ */
 
 int boot_cpu(void);
-#endif
 
 #endif /* CPU_X86_LAPIC_H */
diff --git a/src/include/delay.h b/src/include/delay.h
index 0333879c34..676579b6ae 100644
--- a/src/include/delay.h
+++ b/src/include/delay.h
@@ -1,8 +1,6 @@
 #ifndef DELAY_H
 #define DELAY_H
 
-#if !defined( __ROMCC__)
-
 #if CONFIG_HAVE_INIT_TIMER
 void init_timer(void);
 #else
@@ -12,6 +10,4 @@ void init_timer(void);
 void udelay(unsigned usecs);
 void mdelay(unsigned msecs);
 void delay(unsigned secs);
-
-#endif
 #endif /* DELAY_H */
diff --git a/src/include/ehci.h b/src/include/ehci.h
index 29347f9911..7ec9810f62 100644
--- a/src/include/ehci.h
+++ b/src/include/ehci.h
@@ -25,7 +25,6 @@
 
 #define EHCI_BAR_INDEX		0x10
 
-#ifndef __ROMCC__
 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 
 /* Section 2.2 Host Controller Capability Registers */
@@ -201,4 +200,3 @@ struct ehci_dbg_port {
 #define DBGP_EPADDR(dev, ep)	(((dev)<<8)|(ep))
 } __attribute__ ((packed));
 #endif
-#endif
diff --git a/src/include/ip_checksum.h b/src/include/ip_checksum.h
index de26fa06cc..a1e0ffabd1 100644
--- a/src/include/ip_checksum.h
+++ b/src/include/ip_checksum.h
@@ -1,8 +1,5 @@
 #ifndef IP_CHECKSUM_H
 #define IP_CHECKSUM_H
-
-#ifndef __ROMCC__
 unsigned long compute_ip_checksum(void *addr, unsigned long length);
 unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned long new);
-#endif
 #endif /* IP_CHECKSUM_H */
diff --git a/src/include/lib.h b/src/include/lib.h
index 40c76f2db0..1f71d35880 100644
--- a/src/include/lib.h
+++ b/src/include/lib.h
@@ -22,7 +22,6 @@
 #ifndef __LIB_H__
 #define __LIB_H__
 #include <stdint.h>
-#ifndef __ROMCC__ /* romcc doesn't support prototypes. */
 
 #ifndef __PRE_RAM__ /* Conflicts with inline function in arch/io.h */
 /* Defined in src/lib/clog2.c */
@@ -43,8 +42,10 @@ void quick_ram_check(void);
 /* Defined in src/lib/stack.c */
 int checkstack(void *top_of_stack, int core);
 
+#ifndef __PRE_RAM__ // fails in bootblock compiled with romcc
 /* currently defined by a ldscript */
 extern unsigned char _estack[];
+#endif
 
 /* Defined in romstage.c */
 #if CONFIG_CPU_AMD_GEODE_LX
@@ -53,5 +54,4 @@ void cache_as_ram_main(void);
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
 #endif
 
-#endif /* __ROMCC__ */
 #endif /* __LIB_H__ */
diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h
index f8e2b489ed..f4f0dcaab0 100644
--- a/src/include/pc80/i8254.h
+++ b/src/include/pc80/i8254.h
@@ -58,7 +58,5 @@
 #define PPCB_SPKR       0x02    /* Bit 1 */
 #define PPCB_T2GATE     0x01    /* Bit 0 */
 
-#ifndef __ROMCC__
 void setup_i8254(void);
 #endif
-#endif
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index ee1473b71a..29e034838c 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -203,9 +203,7 @@ static inline int get_option(void *dest __attribute__((unused)),
 #define CMOS_POST_BANK_1_MAGIC    0x81
 #define CMOS_POST_BANK_1_OFFSET   (CMOS_POST_OFFSET + 2)
 
-#if !defined(__ROMCC__)
 void cmos_post_log(void);
-#endif
 #endif /* CONFIG_CMOS_POST */
 
 #endif /*  PC80_MC146818RTC_H */
diff --git a/src/include/reset.h b/src/include/reset.h
index 79bf6d5b20..9f117dbda1 100644
--- a/src/include/reset.h
+++ b/src/include/reset.h
@@ -1,9 +1,6 @@
 #ifndef RESET_H
 #define RESET_H
 
-#if !defined( __ROMCC__ )
-/* ROMCC can't do function prototypes... */
-
 #if CONFIG_HAVE_HARD_RESET
 void hard_reset(void);
 #else
@@ -12,4 +9,3 @@ void hard_reset(void);
 void soft_reset(void);
 
 #endif
-#endif
diff --git a/src/include/uart.h b/src/include/uart.h
index 6b8d8e844c..9601bfa7c9 100644
--- a/src/include/uart.h
+++ b/src/include/uart.h
@@ -30,7 +30,7 @@
 #include <uart8250.h>
 #endif
 
-#if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART
+#if CONFIG_CONSOLE_SERIAL_UART
 unsigned char uart_rx_byte(void);
 void uart_tx_byte(unsigned char data);
 void uart_tx_flush(void);
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index d1164c586c..d42e8226e4 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -114,7 +114,6 @@
 /* Line Control Settings */
 #define UART_LCS	CONFIG_TTYS0_LCS
 
-#ifndef __ROMCC__
 #if CONFIG_CONSOLE_SERIAL8250
 unsigned char uart8250_rx_byte(unsigned base_port);
 int uart8250_can_rx_byte(unsigned base_port);
@@ -145,8 +144,6 @@ void oxford_init(void);
 #endif
 #endif
 
-#endif /* __ROMCC__ */
-
 #endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */
 
 #endif /* UART8250_H */
diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
index 8caf361f90..c3b34377fa 100644
--- a/src/include/usbdebug.h
+++ b/src/include/usbdebug.h
@@ -34,7 +34,6 @@ struct ehci_debug_info {
         u8 bufidx;
 };
 
-#ifndef __ROMCC__
 void enable_usbdebug(unsigned int port);
 int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size);
 int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size);
@@ -47,4 +46,3 @@ void usbdebug_tx_byte(struct ehci_debug_info *info, unsigned char data);
 void usbdebug_tx_flush(struct ehci_debug_info *info);
 int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info);
 #endif
-#endif
diff --git a/src/northbridge/intel/e7501/raminit.h b/src/northbridge/intel/e7501/raminit.h
index df0e9291a3..05c3889aa2 100644
--- a/src/northbridge/intel/e7501/raminit.h
+++ b/src/northbridge/intel/e7501/raminit.h
@@ -15,8 +15,6 @@ struct mem_controller {
 	uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL];
 };
 
-#ifndef __ROMCC__
 void sdram_initialize(int controllers, const struct mem_controller *ctrl);
-#endif
 
 #endif /* RAMINIT_H */
diff --git a/src/northbridge/intel/i3100/raminit.h b/src/northbridge/intel/i3100/raminit.h
index 03e145826a..ea6c60f1aa 100644
--- a/src/northbridge/intel/i3100/raminit.h
+++ b/src/northbridge/intel/i3100/raminit.h
@@ -30,8 +30,6 @@ struct mem_controller {
 	u16 channel1[DIMM_SOCKETS];
 };
 
-#ifndef __ROMCC__
 void sdram_initialize(int controllers, const struct mem_controller *ctrl);
-#endif
 
 #endif
diff --git a/src/southbridge/amd/cs5535/cs5535.h b/src/southbridge/amd/cs5535/cs5535.h
index 0db7c17551..0b435637ee 100644
--- a/src/southbridge/amd/cs5535/cs5535.h
+++ b/src/southbridge/amd/cs5535/cs5535.h
@@ -115,7 +115,7 @@
 /* Flash Memory Mask values */
 #define FLASH_MEM_4K		0xFFFFF000
 
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__)
 #if defined(__PRE_RAM__)
 void cs5535_disable_internal_uart(void);
 #else
diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h
index 84738a212f..c193d9d500 100644
--- a/src/southbridge/amd/cs5536/cs5536.h
+++ b/src/southbridge/amd/cs5536/cs5536.h
@@ -442,7 +442,7 @@
 #define FLASH_IO_128B		0x0000FF80
 #define FLASH_IO_256B		0x0000FF00
 
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__)
 #if defined(__PRE_RAM__)
 void cs5536_setup_onchipuart(int uart);
 void cs5536_disable_internal_uart(void);
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 7f64571c4b..39048662db 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -56,7 +56,7 @@
 void intel_pch_finalize_smm(void);
 #endif
 
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__)
 #if !defined(__PRE_RAM__)
 #if !defined(__SMM__)
 #include "chip.h"
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 76d5fc7085..e6062c68e8 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -21,26 +21,19 @@
 #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 
-#if !defined(__ASSEMBLER__)
+#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
 #if !defined(__PRE_RAM__)
-#if !defined(__ACPI__) /* dsdt include */
-
 #include <arch/io.h>
 #include <device/device.h>
 #include "chip.h"
-
 void i82371eb_enable(device_t dev);
 void i82371eb_hard_reset(void);
-
-#endif
-#endif
-#endif
-
-#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+#else
 void enable_smbus(void);
 int smbus_read_byte(u8 device, u8 address);
 void enable_pm(void);
 #endif
+#endif
 
 /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
  * 'reg' variable, otherwise it clears those bits.
diff --git a/src/southbridge/intel/i82801ax/i82801ax.h b/src/southbridge/intel/i82801ax/i82801ax.h
index ed15bba5fd..f459f2f20a 100644
--- a/src/southbridge/intel/i82801ax/i82801ax.h
+++ b/src/southbridge/intel/i82801ax/i82801ax.h
@@ -24,9 +24,7 @@
 #if !defined(__PRE_RAM__)
 #include "chip.h"
 void i82801ax_enable(device_t dev);
-#endif
-
-#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+#else
 void enable_smbus(void);
 int smbus_read_byte(u8 device, u8 address);
 #endif
diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h
index 202b41cbff..b2ee79c745 100644
--- a/src/southbridge/intel/i82801bx/i82801bx.h
+++ b/src/southbridge/intel/i82801bx/i82801bx.h
@@ -26,7 +26,7 @@
 extern void i82801bx_enable(device_t dev);
 #endif
 
-#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 void enable_smbus(void);
 int smbus_read_byte(u8 device, u8 address);
 #endif
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index dba5bd6d8d..c7d7e77e79 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -31,7 +31,7 @@
 #ifndef I82801DX_H
 #define I82801DX_H
 
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__)
 #if !defined(__PRE_RAM__)
 #include "chip.h"
 extern void i82801dx_enable(device_t dev);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index b5df5d9d32..1064dde8a0 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -37,7 +37,7 @@
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
 
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__)
 #if !defined(__PRE_RAM__)
 #include "chip.h"
 extern void i82801gx_enable(device_t dev);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 7246739bb5..21933b4660 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -21,7 +21,6 @@
 #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H
 #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H
 
-
 /*
  * Lynx Point PCH PCI Devices:
  *
@@ -125,7 +124,7 @@ struct rcba_config_instruction
 	u32 or_value;
 };
 
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__)
 void pch_config_rcba(const struct rcba_config_instruction *rcba_config);
 int pch_silicon_revision(void);
 int pch_silicon_type(void);
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index 5454d79f9d..4fb3391079 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -33,9 +33,7 @@
 void mcp55_enable(device_t dev);
 extern struct pci_operations mcp55_pci_ops;
 #else
-#if !defined(__ROMCC__)
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
 #endif
-#endif
 
 #endif
diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h
index 6c1e7e2add..6085ab5a29 100644
--- a/src/southbridge/sis/sis966/sis966.h
+++ b/src/southbridge/sis/sis966/sis966.h
@@ -35,8 +35,6 @@
 #define DEBUG_USB 0
 #define DEBUG_USB2 0
 
-#if !defined(__ROMCC__)
 void sis966_enable(device_t dev);
-#endif
 
 #endif /* SIS966_H */
diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h
index b43ce3cb3e..3cca58d9ed 100644
--- a/src/southbridge/via/vt8237r/vt8237r.h
+++ b/src/southbridge/via/vt8237r/vt8237r.h
@@ -145,7 +145,6 @@ __attribute__ ((packed))
 
 
 #ifdef __PRE_RAM__
-#ifndef __ROMCC__
 u8 smbus_read_byte(u8 dimm, u8 offset);
 void smbus_write_byte(u8 dimm, u8 offset, u8 data);
 void enable_smbus(void);
@@ -155,7 +154,6 @@ void vt8237_sb_enable_fid_vid(void);
 void enable_rom_decode(void);
 void vt8237_early_spi_init(void);
 int vt8237_early_network_init(struct vt8237_network_rom *rom);
-#endif
 #else
 void writeback(device_t dev, u16 where, u8 what);
 void dump_south(device_t dev);
diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h
index 0616c2af40..5ec6188eae 100644
--- a/src/superio/ite/it8712f/it8712f.h
+++ b/src/superio/ite/it8712f/it8712f.h
@@ -35,11 +35,8 @@
 #define IT8712F_GAME 0x09 /* GAME port */
 #define IT8712F_IR   0x0a /* Consumer IR */
 
-#ifndef __ROMCC__
 void it8712f_kill_watchdog(void);
 void it8712f_enable_serial(device_t dev, u16 iobase);
 void it8712f_24mhz_clkin(void);
 void it8712f_enable_3vsbsw(void);
 #endif
-
-#endif
diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h
index be9f720212..6657db4158 100644
--- a/src/superio/ite/it8716f/it8716f.h
+++ b/src/superio/ite/it8716f/it8716f.h
@@ -41,7 +41,7 @@
 void init_ec(u16 base);
 #endif
 
-#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 void it8716f_disable_dev(device_t dev);
 void it8716f_enable_dev(device_t dev, u16 iobase);
 void it8716f_enable_serial(device_t dev, u16 iobase);
diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h
index 4da5af5d4f..527d1c2409 100644
--- a/src/superio/ite/it8718f/it8718f.h
+++ b/src/superio/ite/it8718f/it8718f.h
@@ -33,7 +33,7 @@
 #define IT8718F_GPIO 0x07 /* GPIO */
 #define IT8718F_IR   0x0a /* Consumer IR */
 
-#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 void it8718f_24mhz_clkin(void);
 void it8718f_disable_reboot(void);
 void it8718f_enable_serial(device_t dev, u16 iobase);
diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h
index cca404af14..25300e6659 100644
--- a/src/superio/ite/it8721f/it8721f.h
+++ b/src/superio/ite/it8721f/it8721f.h
@@ -32,7 +32,7 @@
 #define IT8721F_GPIO 0x07 /* GPIO */
 #define IT8721F_IR   0x0a /* Consumer IR */
 
-#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 void it8721f_24mhz_clkin(void);
 void it8721f_disable_reboot(void);
 void it8721f_enable_serial(device_t dev, u16 iobase);
diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h
index 343d9b36a8..f881d7a92a 100644
--- a/src/superio/ite/it8772f/it8772f.h
+++ b/src/superio/ite/it8772f/it8772f.h
@@ -105,7 +105,6 @@
 #define GPIO_REG_ENABLE(x)   (0xc0 + (x))
 #define GPIO_REG_OUTPUT(x)   (0xc8 + (x))
 
-#ifndef __ROMCC__
 u8 it8772f_sio_read(u8 index);
 void it8772f_sio_write(u8 index, u8 value);
 void it8772f_enable_serial(device_t dev, u16 iobase);
@@ -116,5 +115,3 @@ void it8772f_ac_resume_southbridge(void);
 void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup,
 			u8 output, u8 enable);
 #endif
-
-#endif
diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h
index 7208c8edda..73c1fbcd76 100644
--- a/src/superio/nsc/pc87417/pc87417.h
+++ b/src/superio/nsc/pc87417/pc87417.h
@@ -114,7 +114,7 @@
 #define PC87417_XSCNF		0x15
 #define PC87417_XWBCNF		0x16
 
-#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 void pc87417_enable_serial(device_t dev, u16 iobase);
 void pc87417_enable_dev(device_t dev);
 #endif
diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h
index deab7ce106..c982603315 100644
--- a/src/superio/winbond/w83627ehg/w83627ehg.h
+++ b/src/superio/winbond/w83627ehg/w83627ehg.h
@@ -54,7 +54,7 @@
 #define W83627EHG_GPIO4	((2 << 8) | W83627EHG_GPIO_SUSLED_V)
 #define W83627EHG_GPIO5	((3 << 8) | W83627EHG_GPIO_SUSLED_V)
 
-#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 void w83627ehg_enable_dev(device_t dev, u16 iobase);
 void w83627ehg_disable_dev(device_t dev);
 void w83627ehg_enable_serial(device_t dev, u16 iobase);
diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h
index 423ba8f94d..468cb55b43 100644
--- a/src/superio/winbond/w83627hf/w83627hf.h
+++ b/src/superio/winbond/w83627hf/w83627hf.h
@@ -113,7 +113,7 @@
 #define W83627HF_XSCNF		0x15
 #define W83627HF_XWBCNF		0x16
 
-#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+#if defined(__PRE_RAM__)
 void w83627hf_disable_dev(device_t dev);
 void w83627hf_enable_dev(device_t dev, u16 iobase);
 void w83627hf_enable_serial(device_t dev, u16 iobase);
diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h
index 741d5b2122..7e353e23ce 100644
--- a/src/superio/winbond/w83697hf/w83697hf.h
+++ b/src/superio/winbond/w83697hf/w83697hf.h
@@ -32,8 +32,5 @@
 #define W83697HF_ACPI           10   /* ACPI */
 #define W83697HF_HWM            11   /* Hardware monitor */
 
-#ifndef __ROMCC__
 void w83697hf_set_clksel_48(device_t);
 #endif
-
-#endif