diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-22 15:38:37 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-23 19:10:21 +0200 |
| commit | 3f22abb0a7260d0bdbffff6b1f459be6c55d042f (patch) | |
| tree | af0c18d1c02de34b38f71f8738ac45700b1d5706 /src | |
| parent | b37d01d3093d45528b1447d792d88f85607595ca (diff) | |
intel/haswell post-car: Minor fix on MTRR setting
Change-Id: I65f0ad430bdcc2065c1e873743da04201a68d9c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15796
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 8b15ed546e..a05d570ac8 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -69,7 +69,7 @@ static inline u32 *stack_push(u32 *stack, u32 value) * cache-as-ram is torn down as well as the MTRR settings to use. */ static void *setup_romstage_stack_after_car(void) { - unsigned long top_of_stack; + uintptr_t top_of_stack; int num_mtrrs; u32 *slot; u32 mtrr_mask_upper; @@ -82,7 +82,7 @@ static void *setup_romstage_stack_after_car(void) /* The upper bits of the MTRR mask need to set according to the number * of physical address bits. */ - mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; + mtrr_mask_upper = (1 << (cpu_phys_address_size() - 32)) - 1; /* The order for each MTRR is value then base with upper 32-bits of * each value coming before the lower 32-bits. The reasoning for |