diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-06-20 20:29:29 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-06-21 05:51:35 +0000 |
| commit | 3a183bc03fbd401685e4e0d40ea91abe8c0f6530 (patch) | |
| tree | b0875157703ea5da332dcbd3df6a0cf27ab813b8 /src | |
| parent | c1ef4f3356be9440e981e23914bff03a98f1d89e (diff) | |
meteorlake: Rename `SOC_INTEL_METEORLAKE_U_P` as per latest EDS
This patch renames config `SOC_INTEL_METEORLAKE_U_P` to
`SOC_INTEL_METEORLAKE_U_H` as per Intel Meteor Lake Processor EDS
version 1.3.1 (doc number: 640228).
With new branding, the MTL-U/H-Processor Line offered in a 1-chip platform that includes the Compute, SOC, GT, and IOE tile on the
same package.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I032be650bbfef0bf0ef86bb37417b1d854303501
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75931
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/rex/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/mtlrvp/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 12 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 2 |
4 files changed, 11 insertions, 7 deletions
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 0fb4176af2..407cccc28f 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -39,7 +39,7 @@ config BOARD_GOOGLE_BASEBOARD_REX select HAVE_SLP_S0_GATE select MAINBOARD_HAS_CHROMEOS select MEMORY_SOLDERDOWN - select SOC_INTEL_METEORLAKE_U_P + select SOC_INTEL_METEORLAKE_U_H select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index e27eed9990..8a5908519d 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -19,7 +19,7 @@ config BOARD_INTEL_MTLRVP_COMMON select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT select SOC_INTEL_CSE_LITE_SKU - select SOC_INTEL_METEORLAKE_U_P + select SOC_INTEL_METEORLAKE_U_H config BOARD_INTEL_MTLRVP_P select BOARD_INTEL_MTLRVP_COMMON diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 0bcbcf25d0..7e1353a9a3 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -5,18 +5,22 @@ config SOC_INTEL_METEORLAKE type using the `SOC_INTEL_METEORLAKE_*` options instead of selecting this option directly. -config SOC_INTEL_METEORLAKE_U_P +config SOC_INTEL_METEORLAKE_U_H bool select SOC_INTEL_METEORLAKE help - Choose this option if your mainboard has a MTL-U (15W) or MTL-P (28W) SoC. - Note, MTL-U/P SoC combines Compute, GFX, SoC and IOE die. + Choose this option if your mainboard has a MTL-U (9W or 15W) + or MTL-H (28W or 45W) SoC. + + Note, the MTL-U/H-Processor Line offered in a 1-Chip Platform + that includes the Compute, SOC, GT, and IOE tile on the same + package. config SOC_INTEL_METEORLAKE_S bool select SOC_INTEL_METEORLAKE help - Choose this option if your mainboard has a MTL-S (45W) SoC. + Choose this option if your mainboard has a MTL-S (35W or 65W) SoC. Note, MTL-S SoC combines Compute, GFX, SoC, IOE and PCH die. if SOC_INTEL_METEORLAKE diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index bdc4f7ae61..40b7c47018 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -73,7 +73,7 @@ static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg, } /* PCIE ports */ - if (CONFIG(SOC_INTEL_METEORLAKE_U_P)) { + if (CONFIG(SOC_INTEL_METEORLAKE_U_H)) { m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table()); m_cfg->PchPcieRpEnableMask = 0; /* Don't care about PCH PCIE RP Mask */ pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp, |