diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-07-07 18:45:23 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-07-21 00:49:37 +0000 |
| commit | 39f3c7e1840823c294d7cedf11aed62bdd765141 (patch) | |
| tree | c2bc823a052f1aa7ae09524e8e5cd5b416981fd6 /src | |
| parent | 0b9cfe60b20b91fc172e041d192e48f4548572f5 (diff) | |
google/chell: Convert to a variant of glados
Convert chell to a variant of glados Skylake reference board:
- add chell-specific DPTF, EC config, USB port defs, GPIO config,
NHLT config, PEI data, VBT, SPD data, and devicetree
- add romstage handler to turn on keyboard backlight for boards
so equipped
- remove existing chell board/directory
Test: build/boot google/chell, verify functionality unchanged
from pre-variant configuration
Change-Id: I7dfbafe3afcab7cee7bcb2bf91c6733c07b409c4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
43 files changed, 44 insertions, 1018 deletions
diff --git a/src/mainboard/google/chell/Kconfig b/src/mainboard/google/chell/Kconfig deleted file mode 100644 index 2a8c2375ff..0000000000 --- a/src/mainboard/google/chell/Kconfig +++ /dev/null @@ -1,71 +0,0 @@ -if BOARD_GOOGLE_CHELL - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select BOARD_ROMSIZE_KB_16384 - select DRIVERS_I2C_GENERIC - select DRIVERS_I2C_NAU8825 - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP - select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_LPC - select EC_GOOGLE_CHROMEEC_MEC - select EC_GOOGLE_CHROMEEC_PD - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_SMI_HANDLER - select INTEL_GMA_HAVE_VBT - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select SOC_INTEL_SKYLAKE - select SYSTEM_TYPE_LAPTOP - -config VBOOT - select EC_GOOGLE_CHROMEEC_SWITCHES - select VBOOT_LID_SWITCH - -config IRQ_SLOT_COUNT - int - default 18 - -config MAINBOARD_DIR - string - default "google/chell" - -config MAINBOARD_PART_NUMBER - string - default "Chell" - -config MAINBOARD_FAMILY - string - default "Google_Glados" - -config MAX_CPUS - int - default 8 - -config TPM_PIRQ - hex - default 0x18 # GPP_E0_IRQ - -config INCLUDE_NHLT_BLOBS - bool "Include blobs for audio." - select NHLT_DMIC_2CH - select NHLT_NAU88L25 - select NHLT_SSM4567 - -config EC_GOOGLE_CHROMEEC_BOARDNAME - string - default "chell" - -config EC_GOOGLE_CHROMEEC_PD_BOARDNAME - string - default "chell_pd" - -config GBB_HWID - string - depends on CHROMEOS - default "CHELL TEST 6297" -endif diff --git a/src/mainboard/google/chell/Kconfig.name b/src/mainboard/google/chell/Kconfig.name deleted file mode 100644 index de6ddeac7d..0000000000 --- a/src/mainboard/google/chell/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_CHELL - bool "Chell (HP Chromebook 13 G1)" diff --git a/src/mainboard/google/chell/Makefile.inc b/src/mainboard/google/chell/Makefile.inc deleted file mode 100644 index 91602660c4..0000000000 --- a/src/mainboard/google/chell/Makefile.inc +++ /dev/null @@ -1,33 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += spd - -bootblock-y += bootblock_mainboard.c - -romstage-y += pei_data.c - -bootblock-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c - -ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c - -ramstage-y += mainboard.c -ramstage-y += pei_data.c -ramstage-y += ramstage.c - -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/chell/acpi/ec.asl b/src/mainboard/google/chell/acpi/ec.asl deleted file mode 100644 index 3f5a4ac71f..0000000000 --- a/src/mainboard/google/chell/acpi/ec.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include "../ec.h" -#include "../gpio.h" - -/* Enable EC backed Keyboard Backlight in ACPI */ -#define EC_ENABLE_KEYBOARD_BACKLIGHT - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -/* Enable LID switch and provide wake pin for EC */ -#define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -/* ACPI code for EC functions */ -#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/chell/acpi/superio.asl b/src/mainboard/google/chell/acpi/superio.asl deleted file mode 100644 index 803d2e3f47..0000000000 --- a/src/mainboard/google/chell/acpi/superio.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include "../ec.h" - -#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources -#define SIO_EC_HOST_ENABLE // EC Host Interface Resources -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard - -/* ACPI code for EC SuperIO functions */ -#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/chell/acpi_tables.c b/src/mainboard/google/chell/acpi_tables.c deleted file mode 100644 index e69de29bb2..0000000000 --- a/src/mainboard/google/chell/acpi_tables.c +++ /dev/null diff --git a/src/mainboard/google/chell/bootblock_mainboard.c b/src/mainboard/google/chell/bootblock_mainboard.c deleted file mode 100644 index 627b4e8b08..0000000000 --- a/src/mainboard/google/chell/bootblock_mainboard.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootblock_common.h> -#include <soc/gpio.h> -#include "gpio.h" - -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't do. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - -void bootblock_mainboard_init(void) -{ - early_config_gpio(); -} diff --git a/src/mainboard/google/chell/chromeos.c b/src/mainboard/google/chell/chromeos.c deleted file mode 100644 index 3ff52d918e..0000000000 --- a/src/mainboard/google/chell/chromeos.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <rules.h> -#include <gpio.h> -#include <soc/gpio.h> -#include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> - -#include "gpio.h" - -#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {GPIO_EC_IN_RW, ACTIVE_HIGH, - gpio_get(GPIO_EC_IN_RW), "EC in RW"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} -#endif /* ENV_RAMSTAGE */ - -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), -}; - -void mainboard_chromeos_acpi_generate(void) -{ - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); -} diff --git a/src/mainboard/google/chell/chromeos.fmd b/src/mainboard/google/chell/chromeos.fmd deleted file mode 100644 index 58b612781f..0000000000 --- a/src/mainboard/google/chell/chromeos.fmd +++ /dev/null @@ -1,38 +0,0 @@ -FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x200000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x1ff000 - } - SI_BIOS@0x200000 0xe00000 { - RW_SECTION_A@0x0 0x3f0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 - } - RW_SECTION_B@0x3f0000 0x3f0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 - } - RW_MRC_CACHE@0x7e0000 0x10000 - RW_ELOG@0x7f0000 0x4000 - RW_SHARED@0x7f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x7f8000 0x2000 - RW_NVRAM@0x7fa000 0x6000 - RW_LEGACY(CBFS)@0x800000 0x200000 - WP_RO@0xa00000 0x400000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x3f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x300000 - } - } - } -} diff --git a/src/mainboard/google/chell/cmos.layout b/src/mainboard/google/chell/cmos.layout deleted file mode 100644 index 270f3e0a4c..0000000000 --- a/src/mainboard/google/chell/cmos.layout +++ /dev/null @@ -1,125 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2015 Intel Corporation -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/google/chell/dsdt.asl b/src/mainboard/google/chell/dsdt.asl deleted file mode 100644 index b5a37c68cc..0000000000 --- a/src/mainboard/google/chell/dsdt.asl +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x05, // DSDT revision: ACPI v5.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include <soc/intel/skylake/acpi/platform.asl> - - // global NVS and variables - #include <soc/intel/skylake/acpi/globalnvs.asl> - - // CPU - #include <soc/intel/skylake/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/skylake/acpi/systemagent.asl> - #include <soc/intel/skylake/acpi/pch.asl> - } - - // Dynamic Platform Thermal Framework - #include "acpi/dptf.asl" - } - - // Chrome OS specific - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> - - // Mainboard specific - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/google/chell/ec.c b/src/mainboard/google/chell/ec.c deleted file mode 100644 index 372237800e..0000000000 --- a/src/mainboard/google/chell/ec.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -void mainboard_ec_init(void) -{ - const struct google_chromeec_event_info info = { - .log_events = MAINBOARD_EC_LOG_EVENTS, - .sci_events = MAINBOARD_EC_SCI_EVENTS, - .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, - .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, - }; - - printk(BIOS_DEBUG, "mainboard: EC init\n"); - - google_chromeec_events_init(&info, acpi_is_wakeup_s3()); -} diff --git a/src/mainboard/google/chell/ec.h b/src/mainboard/google/chell/ec.h deleted file mode 100644 index fcb0a70796..0000000000 --- a/src/mainboard/google/chell/ec.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_EC_H -#define MAINBOARD_EC_H - -#include <ec/ec.h> -#include <ec/google/chromeec/ec_commands.h> - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with lid or power button or key press */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -#endif diff --git a/src/mainboard/google/chell/mainboard.c b/src/mainboard/google/chell/mainboard.c deleted file mode 100644 index e2cf9ad601..0000000000 --- a/src/mainboard/google/chell/mainboard.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <console/console.h> -#include <device/device.h> -#include <stdlib.h> -#include <soc/nhlt.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" - -static void mainboard_init(struct device *dev) -{ - mainboard_ec_init(); -} - -static unsigned long mainboard_write_acpi_tables( - struct device *device, unsigned long current, acpi_rsdp_t *rsdp) -{ - uintptr_t start_addr; - uintptr_t end_addr; - struct nhlt *nhlt; - - start_addr = current; - - nhlt = nhlt_init(); - - if (nhlt == NULL) - return start_addr; - - /* 2 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 2)) - printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); - - /* ADI Smart Amps for left and right. */ - if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0)) - printk(BIOS_ERR, "Couldn't add ssm4567.\n"); - - /* NAU88l25 Headset codec. */ - if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1)) - printk(BIOS_ERR, "Couldn't add headset codec.\n"); - - end_addr = nhlt_soc_serialize(nhlt, start_addr); - - if (end_addr != start_addr) - acpi_add_table(rsdp, (void *)start_addr); - - return end_addr; -} - -/* - * mainboard_enable is executed as first thing after - * enumerate_buses(). - */ -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = mainboard_init; - dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/chell/ramstage.c b/src/mainboard/google/chell/ramstage.c deleted file mode 100644 index d22e145357..0000000000 --- a/src/mainboard/google/chell/ramstage.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/ramstage.h> -#include "gpio.h" - -void mainboard_silicon_init_params(SILICON_INIT_UPD *params) -{ - /* Configure pads prior to SiliconInit() in case there's any - * dependencies during hardware initialization. */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -} diff --git a/src/mainboard/google/chell/romstage.c b/src/mainboard/google/chell/romstage.c deleted file mode 100644 index 54b4afa62b..0000000000 --- a/src/mainboard/google/chell/romstage.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <arch/acpi.h> -#include <ec/google/chromeec/ec.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> -#include "spd/spd.h" - -void mainboard_romstage_entry(struct romstage_params *params) -{ - /* Turn on keyboard backlight to indicate we are booting */ - if (params->power_state->prev_sleep_state != ACPI_S3) - google_chromeec_kbbacklight(25); - - /* Fill out PEI DATA */ - mainboard_fill_pei_data(params->pei_data); - mainboard_fill_spd_data(params->pei_data); - /* Initialize memory */ - romstage_common(params); -} - -void mainboard_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) -{ - if (params->pei_data->spd_data[0][0][0] != 0) { - memory_params->MemorySpdPtr00 = - (UINT32)(params->pei_data->spd_data[0][0]); - memory_params->MemorySpdPtr10 = - (UINT32)(params->pei_data->spd_data[1][0]); - } - memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], - sizeof(params->pei_data->dq_map[0])); - memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], - sizeof(params->pei_data->dq_map[1])); - memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], - sizeof(params->pei_data->dqs_map[0])); - memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], - sizeof(params->pei_data->dqs_map[1])); - memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, - sizeof(params->pei_data->RcompResistor)); - memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, - sizeof(params->pei_data->RcompTarget)); - memory_params->MemorySpdDataLen = SPD_LEN; - memory_params->DqPinsInterleaved = FALSE; -} diff --git a/src/mainboard/google/chell/smihandler.c b/src/mainboard/google/chell/smihandler.c deleted file mode 100644 index c8319833c3..0000000000 --- a/src/mainboard/google/chell/smihandler.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <elog.h> -#include <ec/google/chromeec/smm.h> -#include <gpio.h> -#include <soc/iomap.h> -#include <soc/nvs.h> -#include <soc/pm.h> -#include <soc/smm.h> -#include "ec.h" -#include "gpio.h" - -int mainboard_io_trap_handler(int smif) -{ - switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; - break; - default: - return 0; - } - - /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - return 1; -} - -void mainboard_smi_gpi_handler(const struct gpi_status *sts) -{ - if (gpi_status_get(sts, EC_SMI_GPI)) - chromeec_smi_process_events(); -} - -static void mainboard_gpio_smi_sleep(u8 slp_typ) -{ - int i; - - /* Power down the rails on any sleep type. */ - gpio_t active_high_signals[] = { - EN_PP3300_KEPLER, - EN_PP3300_DX_TOUCH, - EN_PP3300_DX_EMMC, - EN_PP1800_DX_EMMC, - EN_PP3300_DX_CAM, - }; - - for (i = 0; i < ARRAY_SIZE(active_high_signals); i++) - gpio_set(active_high_signals[i], 0); -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) - chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, - MAINBOARD_EC_S5_WAKE_EVENTS); - - mainboard_gpio_smi_sleep(slp_typ); -} - -int mainboard_smi_apmc(u8 apmc) -{ - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) - chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, - MAINBOARD_EC_SMI_EVENTS); - return 0; -} diff --git a/src/mainboard/google/chell/spd/empty.spd.hex b/src/mainboard/google/chell/spd/empty.spd.hex deleted file mode 100644 index 9ec39f1ba4..0000000000 --- a/src/mainboard/google/chell/spd/empty.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/chell/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex b/src/mainboard/google/chell/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex deleted file mode 100644 index 4ecefdda47..0000000000 --- a/src/mainboard/google/chell/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -91 20 F1 03 04 12 05 0A 03 11 01 08 09 00 50 05 -78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 -00 80 ca fa 00 00 00 A8 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 -4B 34 45 36 45 33 30 34 45 45 2D 45 47 43 46 20 -20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/chell/spd/spd.c b/src/mainboard/google/chell/spd/spd.c deleted file mode 100644 index 251b6de3cb..0000000000 --- a/src/mainboard/google/chell/spd/spd.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/byteorder.h> -#include <cbfs.h> -#include <console/console.h> -#include <gpio.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> -#include <string.h> - -#include "../gpio.h" -#include "spd.h" - -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, - "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", - banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) -{ - char *spd_file; - size_t spd_file_len; - int spd_index; - - gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - - spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); - printk(BIOS_INFO, "SPD index %d\n", spd_index); - - /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); - spd_index = 1; - } - - /* Assume same memory in both channels */ - spd_index *= SPD_LEN; - memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN); - memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN); - - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) - die("Invalid SPD data."); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); -} diff --git a/src/mainboard/google/chell/spd/spd.h b/src/mainboard/google/chell/spd/spd.h deleted file mode 100644 index c8e7b3304a..0000000000 --- a/src/mainboard/google/chell/spd/spd.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 - -#endif diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 5bed271a13..9ef8736dc2 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -13,6 +13,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_GLADOS select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 @@ -35,6 +36,7 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string + default "Chell" if BOARD_GOOGLE_CHELL default "Glados" if BOARD_GOOGLE_GLADOS config MAINBOARD_FAMILY @@ -43,10 +45,12 @@ config MAINBOARD_FAMILY config VARIANT_DIR string + default "chell" if BOARD_GOOGLE_CHELL default "glados" if BOARD_GOOGLE_GLADOS config DEVICETREE string + default "variants/chell/devicetree.cb" if BOARD_GOOGLE_CHELL default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS config MAX_CPUS @@ -64,14 +68,17 @@ config INCLUDE_NHLT_BLOBS config EC_GOOGLE_CHROMEEC_BOARDNAME string + default "chell" if BOARD_GOOGLE_CHELL default "glados" if BOARD_GOOGLE_GLADOS config EC_GOOGLE_CHROMEEC_PD_BOARDNAME string + default "chell_pd" if BOARD_GOOGLE_CHELL default "glados_pd" if BOARD_GOOGLE_GLADOS config GBB_HWID string depends on CHROMEOS + default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS endif diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name index b1c6db22b9..1f2365437b 100644 --- a/src/mainboard/google/glados/Kconfig.name +++ b/src/mainboard/google/glados/Kconfig.name @@ -1,5 +1,10 @@ comment "Glados" +config BOARD_GOOGLE_CHELL + bool "-> Chell (HP Chromebook 13 G1)" + select BOARD_GOOGLE_BASEBOARD_GLADOS + select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS + config BOARD_GOOGLE_GLADOS bool "-> Glados Skylake Reference Board" select BOARD_GOOGLE_BASEBOARD_GLADOS diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 07f0ff0aca..4f93f61114 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -22,10 +22,16 @@ #include <soc/pei_wrapper.h> #include <soc/romstage.h> #include "spd/spd.h" +#include <variant/ec.h> #include <variant/gpio.h> void mainboard_romstage_entry(struct romstage_params *params) { +#ifdef EC_ENABLE_KEYBOARD_BACKLIGHT + /* Turn on keyboard backlight to indicate we are booting */ + if (params->power_state->prev_sleep_state != ACPI_S3) + google_chromeec_kbbacklight(25); +#endif /* Get SPD index */ gpio_t spd_gpios[] = { GPIO_MEM_CONFIG_0, diff --git a/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex index 5c1332e57c..5c1332e57c 100644 --- a/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex diff --git a/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNN8GTMLAR.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR.spd.hex index c4041702c6..c4041702c6 100644 --- a/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNN8GTMLAR.spd.hex +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR.spd.hex diff --git a/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex index 7c7c8d2026..7c7c8d2026 100644 --- a/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex diff --git a/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex index 2f66a2a14a..2f66a2a14a 100644 --- a/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex diff --git a/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNCLGALAR.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLGALAR.spd.hex index 24c032b61c..24c032b61c 100644 --- a/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNCLGALAR.spd.hex +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLGALAR.spd.hex diff --git a/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex index df2819f1ec..df2819f1ec 100644 --- a/src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex diff --git a/src/mainboard/google/chell/spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex index f2916308d2..f2916308d2 100644 --- a/src/mainboard/google/chell/spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex +++ b/src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex diff --git a/src/mainboard/google/chell/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex index 24167ebd0a..24167ebd0a 100644 --- a/src/mainboard/google/chell/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex +++ b/src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex diff --git a/src/mainboard/google/chell/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex index 7d72967a03..7d72967a03 100644 --- a/src/mainboard/google/chell/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex +++ b/src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex diff --git a/src/mainboard/google/chell/spd/samsung_dimm_K4EBE304EB-EGCF.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4EBE304EB-EGCF.spd.hex index 930d27f39a..930d27f39a 100644 --- a/src/mainboard/google/chell/spd/samsung_dimm_K4EBE304EB-EGCF.spd.hex +++ b/src/mainboard/google/glados/spd/samsung_dimm_K4EBE304EB-EGCF.spd.hex diff --git a/src/mainboard/google/chell/spd/Makefile.inc b/src/mainboard/google/glados/variants/chell/Makefile.inc index ed46a0389e..986bdd8552 100644 --- a/src/mainboard/google/chell/spd/Makefile.inc +++ b/src/mainboard/google/glados/variants/chell/Makefile.inc @@ -14,7 +14,9 @@ ## GNU General Public License for more details. ## -romstage-y += spd.c +romstage-y += variant.c +ramstage-y += variant.c +smm-y += variant.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/chell/board_info.txt b/src/mainboard/google/glados/variants/chell/board_info.txt index be33f44cca..d1630c8d6e 100644 --- a/src/mainboard/google/chell/board_info.txt +++ b/src/mainboard/google/glados/variants/chell/board_info.txt @@ -1,5 +1,5 @@ Vendor name: Google -Board name: Chell Skylake Reference Board +Board name: Chell (HP Chromebook 13 G1) Category: laptop ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/google/chell/data.vbt b/src/mainboard/google/glados/variants/chell/data.vbt Binary files differindex a654a5efd5..a654a5efd5 100644 --- a/src/mainboard/google/chell/data.vbt +++ b/src/mainboard/google/glados/variants/chell/data.vbt diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb index b9d072f8a1..b9d072f8a1 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/glados/variants/chell/devicetree.cb diff --git a/src/mainboard/google/chell/acpi/dptf.asl b/src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl index 68aa8a86b8..ad370982ab 100644 --- a/src/mainboard/google/chell/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl @@ -89,6 +89,3 @@ Name (MPPC, Package () 1000 /* StepSize */ } }) - -/* Include DPTF */ -#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/chell/acpi/usb.asl b/src/mainboard/google/glados/variants/chell/include/variant/acpi/mainboard.asl index aa465fae4f..aa465fae4f 100644 --- a/src/mainboard/google/chell/acpi/usb.asl +++ b/src/mainboard/google/glados/variants/chell/include/variant/acpi/mainboard.asl diff --git a/src/mainboard/google/chell/acpi/mainboard.asl b/src/mainboard/google/glados/variants/chell/include/variant/ec.h index 5d382c4205..be6c0a55d6 100644 --- a/src/mainboard/google/chell/acpi/mainboard.asl +++ b/src/mainboard/google/glados/variants/chell/include/variant/ec.h @@ -13,15 +13,5 @@ * GNU General Public License for more details. */ -#include "../gpio.h" - -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } -} - -/* USB port entries */ -#include "usb.asl" +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h index ebece32f12..ebece32f12 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h diff --git a/src/mainboard/google/chell/pei_data.c b/src/mainboard/google/glados/variants/chell/variant.c index 84f38d9719..da83ed0f7d 100644 --- a/src/mainboard/google/chell/pei_data.c +++ b/src/mainboard/google/glados/variants/chell/variant.c @@ -14,10 +14,13 @@ * GNU General Public License for more details. */ +#include <baseboard/variant.h> +#include <gpio.h> #include <stdint.h> #include <string.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> +#include <variant/gpio.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { @@ -45,3 +48,20 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) memcpy(pei_data->RcompTarget, RcompTarget, sizeof(RcompTarget)); } + +void mainboard_gpio_smi_sleep(void) +{ + int i; + + /* Power down the rails on any sleep type. */ + gpio_t active_high_signals[] = { + EN_PP3300_KEPLER, + EN_PP3300_DX_TOUCH, + EN_PP3300_DX_EMMC, + EN_PP1800_DX_EMMC, + EN_PP3300_DX_CAM, + }; + + for (i = 0; i < ARRAY_SIZE(active_high_signals); i++) + gpio_set(active_high_signals[i], 0); +} |