diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-07-23 14:57:50 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-07-24 11:13:41 +0000 |
| commit | 39b53d9622cdcdbd199e75aa0ae479b579646d07 (patch) | |
| tree | bbdbfe096a2d305f92e04940eb18aecdbafa2c9d /src | |
| parent | eeaf5692576f2947c45d31ee3f99434fafa33817 (diff) | |
soc/intel/common/block: Add space before comment delimiter
Update comment section to add space before comment delimiter to
follow coding style.
Change-Id: I883aeaa9839fa96fd7baf0c771b394409b18ddca
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56547
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/itss.h | 18 |
2 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 784e8ca0ae..5f39507373 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -515,7 +515,7 @@ find_llc_subleaf: set_eviction_mask: mov %ebx, %edi /* back up number of ways */ - mov %eax, %esi /* back up the non-eviction mask*/ + mov %eax, %esi /* back up the non-eviction mask */ #if CONFIG(CAR_HAS_SF_MASKS) /* * SF mask is programmed with the double number of bits than diff --git a/src/soc/intel/common/block/include/intelblocks/itss.h b/src/soc/intel/common/block/include/intelblocks/itss.h index 286304c031..4d26b25b4d 100644 --- a/src/soc/intel/common/block/include/intelblocks/itss.h +++ b/src/soc/intel/common/block/include/intelblocks/itss.h @@ -3,23 +3,23 @@ #ifndef SOC_INTEL_COMMON_BLOCK_ITSS_H #define SOC_INTEL_COMMON_BLOCK_ITSS_H -/* PIRQA Routing Control Register*/ +/* PIRQA Routing Control Register */ #define PCR_ITSS_PIRQA_ROUT 0x3100 -/* PIRQB Routing Control Register*/ +/* PIRQB Routing Control Register */ #define PCR_ITSS_PIRQB_ROUT 0x3101 -/* PIRQC Routing Control Register*/ +/* PIRQC Routing Control Register */ #define PCR_ITSS_PIRQC_ROUT 0x3102 -/* PIRQD Routing Control Register*/ +/* PIRQD Routing Control Register */ #define PCR_ITSS_PIRQD_ROUT 0x3103 -/* PIRQE Routing Control Register*/ +/* PIRQE Routing Control Register */ #define PCR_ITSS_PIRQE_ROUT 0x3104 -/* PIRQF Routing Control Register*/ +/* PIRQF Routing Control Register */ #define PCR_ITSS_PIRQF_ROUT 0x3105 -/* PIRQG Routing Control Register*/ +/* PIRQG Routing Control Register */ #define PCR_ITSS_PIRQG_ROUT 0x3106 -/* PIRQH Routing Control Register*/ +/* PIRQH Routing Control Register */ #define PCR_ITSS_PIRQH_ROUT 0x3107 -/* ITSS Interrupt polarity control*/ +/* ITSS Interrupt polarity control */ #define PCR_ITSS_IPC0_CONF 0x3200 /* ITSS Power reduction control */ #define PCR_ITSS_ITSSPRC 0x3300 |