summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorMichael Niewöhner <foss@mniewoehner.de>2021-10-05 22:22:21 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-10-21 20:03:14 +0000
commit38107fa80eb81fe5077dbee0dd9a46618c71a196 (patch)
treed8f040f30350f52a5ccc8fcc63ef37042e08ff46 /src
parent679f4fa46578267989b55635e50ef500f7327338 (diff)
acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
Some elements in the ACPI CPPC table allow static DWORDs. Instead of using a fake register resource, use a tagged union with the two types "register" and "DWORD" and respective macros for CPPC table entries. Test: dumped SSDT before and after do not differ. Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
-rw-r--r--src/acpi/acpigen.c12
-rw-r--r--src/cpu/intel/common/common.h1
-rw-r--r--src/cpu/intel/common/common_init.c49
-rw-r--r--src/include/acpi/acpigen.h35
-rw-r--r--src/soc/amd/cezanne/cppc.c42
-rw-r--r--src/soc/amd/cezanne/include/soc/cppc.h1
6 files changed, 73 insertions, 67 deletions
diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c
index e0892e654f..37bfec1654 100644
--- a/src/acpi/acpigen.c
+++ b/src/acpi/acpigen.c
@@ -1798,13 +1798,11 @@ void acpigen_write_CPPC_package(const struct cppc_config *config)
acpigen_write_byte(config->version);
for (i = 0; i < max; ++i) {
- const acpi_addr_t *reg = &(config->regs[i]);
- if (reg->space_id == ACPI_ADDRESS_SPACE_MEMORY &&
- reg->bit_width == 32 && reg->access_size == ACPI_ACCESS_SIZE_UNDEFINED) {
- acpigen_write_dword(reg->addrl);
- } else {
- acpigen_write_register_resource(reg);
- }
+ const cppc_entry_t *entry = &config->entries[i];
+ if (entry->type == CPPC_TYPE_DWORD)
+ acpigen_write_dword(entry->dword);
+ else
+ acpigen_write_register_resource(&entry->reg);
}
acpigen_pop_len();
}
diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h
index fdacd1f74b..909f75ac40 100644
--- a/src/cpu/intel/common/common.h
+++ b/src/cpu/intel/common/common.h
@@ -4,6 +4,7 @@
#define _CPU_INTEL_COMMON_H
#include <types.h>
+#include <acpi/acpigen.h>
void set_vmx_and_lock(void);
void set_feature_ctrl_vmx(void);
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index 6203922fd8..765a174dd1 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -105,42 +105,35 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
{
config->version = version;
- config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8);
- config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_PLATFORM_INFO, 8, 8);
- config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8);
- config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8);
- config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8);
- config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 16, 8);
- config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 0, 8);
- config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 8, 8);
- config->regs[CPPC_PERF_REDUCE_TOLERANCE] = ACPI_REG_UNSUPPORTED;
- config->regs[CPPC_TIME_WINDOW] = ACPI_REG_UNSUPPORTED;
- config->regs[CPPC_COUNTER_WRAP] = ACPI_REG_UNSUPPORTED;
- config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(IA32_MPERF, 0, 64);
- config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(IA32_APERF, 0, 64);
- config->regs[CPPC_PERF_LIMITED] = ACPI_REG_MSR(IA32_HWP_STATUS, 2, 1);
- config->regs[CPPC_ENABLE] = ACPI_REG_MSR(IA32_PM_ENABLE, 0, 1);
+ config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8);
+ config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_PLATFORM_INFO, 8, 8);
+ config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8);
+ config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8);
+ config->entries[CPPC_GUARANTEED_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8);
+ config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(IA32_HWP_REQUEST, 16, 8);
+ config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(IA32_HWP_REQUEST, 0, 8);
+ config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(IA32_HWP_REQUEST, 8, 8);
+ config->entries[CPPC_PERF_REDUCE_TOLERANCE] = CPPC_UNSUPPORTED;
+ config->entries[CPPC_TIME_WINDOW] = CPPC_UNSUPPORTED;
+ config->entries[CPPC_COUNTER_WRAP] = CPPC_UNSUPPORTED;
+ config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(IA32_MPERF, 0, 64);
+ config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(IA32_APERF, 0, 64);
+ config->entries[CPPC_PERF_LIMITED] = CPPC_REG_MSR(IA32_HWP_STATUS, 2, 1);
+ config->entries[CPPC_ENABLE] = CPPC_REG_MSR(IA32_PM_ENABLE, 0, 1);
if (version < 2)
return;
- config->regs[CPPC_AUTO_SELECT] = (acpi_addr_t){
- .space_id = ACPI_ADDRESS_SPACE_MEMORY,
- .bit_width = 32,
- .bit_offset = 0,
- .access_size = ACPI_ACCESS_SIZE_UNDEFINED,
- .addrl = 1,
- };
-
- config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_MSR(IA32_HWP_REQUEST, 32, 10);
- config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 24, 8);
- config->regs[CPPC_REF_PERF] = ACPI_REG_UNSUPPORTED;
+ config->entries[CPPC_AUTO_SELECT] = CPPC_DWORD(1);
+ config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG_MSR(IA32_HWP_REQUEST, 32, 10);
+ config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(IA32_HWP_REQUEST, 24, 8);
+ config->entries[CPPC_REF_PERF] = CPPC_UNSUPPORTED;
if (version < 3)
return;
- config->regs[CPPC_LOWEST_FREQ] = ACPI_REG_UNSUPPORTED;
- config->regs[CPPC_NOMINAL_FREQ] = ACPI_REG_UNSUPPORTED;
+ config->entries[CPPC_LOWEST_FREQ] = CPPC_UNSUPPORTED;
+ config->entries[CPPC_NOMINAL_FREQ] = CPPC_UNSUPPORTED;
}
void set_aesni_lock(void)
diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h
index 3af0959cfd..463c16d2b2 100644
--- a/src/include/acpi/acpigen.h
+++ b/src/include/acpi/acpigen.h
@@ -265,24 +265,37 @@ enum cppc_fields {
CPPC_MAX_FIELDS_VER_3,
};
+typedef struct cppc_entry {
+ enum { CPPC_TYPE_REG, CPPC_TYPE_DWORD } type;
+ union {
+ acpi_addr_t reg;
+ uint32_t dword;
+ };
+} cppc_entry_t;
+
+#define CPPC_DWORD(_dword) \
+ (cppc_entry_t){ \
+ .type = CPPC_TYPE_DWORD, \
+ .dword = _dword, \
+ }
+
+#define CPPC_REG(_reg) \
+ (cppc_entry_t){ \
+ .type = CPPC_TYPE_REG, \
+ .reg = _reg, \
+ }
+
+#define CPPC_REG_MSR(address, offset, width) CPPC_REG(ACPI_REG_MSR(address, offset, width))
+#define CPPC_UNSUPPORTED CPPC_REG(ACPI_REG_UNSUPPORTED)
+
struct cppc_config {
u32 version; /* must be 1, 2, or 3 */
/*
* The generic acpi_addr_t structure is being used, though
* anything besides PPC or FFIXED generally requires checking
* if the OS has advertised support for it (via _OSC).
- *
- * NOTE: some fields permit DWORDs to be used. If you
- * provide a System Memory register with all zeros (which
- * represents unsupported) then this will be used as-is.
- * Otherwise, a System Memory register with a 32-bit
- * width will be converted into a DWORD field (the value
- * of which will be the value of 'addrl'. Any other use
- * of System Memory register is currently undefined.
- * (i.e., if you have an actual need for System Memory
- * then you'll need to adjust this kludge).
*/
- acpi_addr_t regs[CPPC_MAX_FIELDS_VER_3];
+ cppc_entry_t entries[CPPC_MAX_FIELDS_VER_3];
};
void acpigen_write_return_integer(uint64_t arg);
diff --git a/src/soc/amd/cezanne/cppc.c b/src/soc/amd/cezanne/cppc.c
index 9d681c6ba7..1afa26f3e1 100644
--- a/src/soc/amd/cezanne/cppc.c
+++ b/src/soc/amd/cezanne/cppc.c
@@ -15,35 +15,35 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
{
config->version = version;
- config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
- config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
- config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
- config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
- config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_UNSUPPORTED;
- config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
- config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
- config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
- config->regs[CPPC_PERF_REDUCE_TOLERANCE] = ACPI_REG_UNSUPPORTED;
- config->regs[CPPC_TIME_WINDOW] = ACPI_REG_UNSUPPORTED;
- config->regs[CPPC_COUNTER_WRAP] = ACPI_REG_UNSUPPORTED;
- config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
- config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
- config->regs[CPPC_PERF_LIMITED] = ACPI_REG_MSR(MSR_CPPC_STATUS, 1, 1);
- config->regs[CPPC_ENABLE] = ACPI_REG_MSR(MSR_CPPC_ENABLE, 0, 1);
+ config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
+ config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
+ config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
+ config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
+ config->entries[CPPC_GUARANTEED_PERF] = CPPC_UNSUPPORTED;
+ config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
+ config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
+ config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
+ config->entries[CPPC_PERF_REDUCE_TOLERANCE] = CPPC_UNSUPPORTED;
+ config->entries[CPPC_TIME_WINDOW] = CPPC_UNSUPPORTED;
+ config->entries[CPPC_COUNTER_WRAP] = CPPC_UNSUPPORTED;
+ config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
+ config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
+ config->entries[CPPC_PERF_LIMITED] = CPPC_REG_MSR(MSR_CPPC_STATUS, 1, 1);
+ config->entries[CPPC_ENABLE] = CPPC_REG_MSR(MSR_CPPC_ENABLE, 0, 1);
if (version < 2)
return;
- config->regs[CPPC_AUTO_SELECT] = ACPI_REG_UNSUPPORTED;
- config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_UNSUPPORTED;
- config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
- config->regs[CPPC_REF_PERF] = ACPI_REG_UNSUPPORTED;
+ config->entries[CPPC_AUTO_SELECT] = CPPC_UNSUPPORTED;
+ config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_UNSUPPORTED;
+ config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
+ config->entries[CPPC_REF_PERF] = CPPC_UNSUPPORTED;
if (version < 3)
return;
- config->regs[CPPC_LOWEST_FREQ] = ACPI_REG_UNSUPPORTED;
- config->regs[CPPC_NOMINAL_FREQ] = ACPI_REG_UNSUPPORTED;
+ config->entries[CPPC_LOWEST_FREQ] = CPPC_UNSUPPORTED;
+ config->entries[CPPC_NOMINAL_FREQ] = CPPC_UNSUPPORTED;
}
diff --git a/src/soc/amd/cezanne/include/soc/cppc.h b/src/soc/amd/cezanne/include/soc/cppc.h
index 60a5efd334..e2f4daaf49 100644
--- a/src/soc/amd/cezanne/include/soc/cppc.h
+++ b/src/soc/amd/cezanne/include/soc/cppc.h
@@ -4,6 +4,7 @@
#define _CPU_AMD_COMMON_H
#include <types.h>
+#include <acpi/acpigen.h>
struct cppc_config;
void cpu_init_cppc_config(struct cppc_config *config, u32 version);