diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2019-02-15 05:36:50 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-02-19 22:00:40 +0000 |
| commit | 34745f613f4a2970b2298bd76bfaf737229a4a3a (patch) | |
| tree | 4db539a93bfdd12f843b366673fae26a6eb45ae7 /src | |
| parent | 04aae87da74a8c47abb46958384ef5632fec1e4a (diff) | |
soc/intel/common: Add whiskeylake celeron v-0 support
New whiskeylake v-0 stepping have changed the graphics device id from
0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the
CPUID was changed from 806EB to 806EC, include that as well.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6
Reviewed-on: https://review.coreboot.org/c/31433
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/device/pci_ids.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/report_platform.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/mp_init.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/graphics/graphics.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/mp_init.h | 1 |
5 files changed, 5 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 751cca0289..00309612b3 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2969,6 +2969,7 @@ #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500 0x5a85 #define PCI_DEVICE_ID_INTEL_GLK_IGD 0x3184 #define PCI_DEVICE_ID_INTEL_GLK_IGD_EU12 0x3185 +#define PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1 0x3EA1 #define PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1 0x3EA0 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1 0x5A51 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2 0x5A59 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 8839816591..e61c7f4a93 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -37,6 +37,7 @@ static struct { { CPUID_CANNONLAKE_C0, "Cannonlake C0" }, { CPUID_CANNONLAKE_D0, "Cannonlake D0" }, { CPUID_COFFEELAKE_D0, "Coffeelake D0" }, + { CPUID_WHISKEYLAKE_V0, "Whiskeylake V0"}, { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0"}, { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" }, }; diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 5f5c8cf11f..7deaaa8096 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -70,6 +70,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, + { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_V0 }, { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 19a78e7488..8eebd1241c 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -118,6 +118,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, PCI_DEVICE_ID_INTEL_GLK_IGD, PCI_DEVICE_ID_INTEL_GLK_IGD_EU12, + PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1, PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM, PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index b0fd857350..fca6ca59fd 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -37,6 +37,7 @@ #define CPUID_APOLLOLAKE_E0 0x506ca #define CPUID_GLK_A0 0x706a0 #define CPUID_GLK_B0 0x706a1 +#define CPUID_WHISKEYLAKE_V0 0x806ec #define CPUID_WHISKEYLAKE_W0 0x806eb #define CPUID_COFFEELAKE_D0 0x806ea #define CPUID_COFFEELAKE_U0 0x906ea |