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authorShon Wang <shon.wang@quanta.corp-partner.google.com>2024-06-25 16:01:00 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-06-27 14:36:37 +0000
commit2ebfb79d336c864eb93619fb2980e5b9fc90b014 (patch)
tree8b5ccdf7bf01220c265a16d38d896cb0965d4332 /src
parentd5658fd7c02d590fad8d6556872143dc1e7b6ccf (diff)
mb/google/brask/var/bujia: Configure Serial IO UARTs Mode
This patch configures Serial IO UARTs mode as below. UART0 and UART1 in PCI mode and keep UART2 disable as per hardware design. BUG=b:338917836 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83205 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/brya/variants/bujia/overridetree.cb6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb
index 252d82f8a5..4255296ff6 100644
--- a/src/mainboard/google/brya/variants/bujia/overridetree.cb
+++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb
@@ -46,6 +46,12 @@ chip soc/intel/alderlake
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
}"
+ register "serial_io_uart_mode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoPci,
+ [PchSerialIoIndexUART1] = PchSerialIoPci,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,