diff options
| author | Rory Liu <rory.liu@quanta.corp-partner.google.com> | 2021-12-30 11:36:45 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-03 16:15:39 +0000 |
| commit | 2a4858afed4c8618182a78a6de965d1cad6e8630 (patch) | |
| tree | 49e51696970ef7118e9caf94aa923d24a5c4706f /src | |
| parent | 69107c149b458be1ba7500d59686cdea066a0cae (diff) | |
mb/google/brya/var/brask: Change I2C/DDC signals
The latest schematics changes the EN_PP3300_SSD from GPP_D11 to GPP_F14,
I2C/DDC signals from GPP_E22/E23 to GPP_D11/D12.
BUG=b:206602609
TEST=build pass
Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com>
Change-Id: I1e4aa6c540806c34b4a642f7813de0a64c6ea2b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brask/gpio.c | 24 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/brask/gpio.c | 4 |
2 files changed, 14 insertions, 14 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 5ad8e46bd7..42c0275875 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -139,10 +139,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), - /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ - PAD_NC(GPP_D12, NONE), + /* D11 : ISH_SPI_MISO ==> DDIA_DP_CTRLCLK */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + /* D12 : ISH_SPI_MOSI ==> DDIA_DP_CTRLDATA */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), /* D13 : ISH_UART0_RXD ==> TP97 */ PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> TP93 */ @@ -202,10 +202,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_RX_STRAP */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), - /* E22 : DDPA_CTRLCLK ==> DDIA_DP_CTRLCLK */ - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), - /* E23 : DDPA_CTRLDATA ==> DDIA_DP_CTRLDATA */ - PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + /* E22 : DDPA_CTRLCLK ==> NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> NC */ + PAD_NC(GPP_E23, NONE), /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), @@ -235,8 +235,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), - /* F14 : GSXDIN ==> NC */ - PAD_NC(GPP_F14, NONE), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), /* F15 : GSXSRESET# ==> FPMCU_INT_L */ PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT), /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ @@ -386,10 +386,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/brask/gpio.c b/src/mainboard/google/brya/variants/brask/gpio.c index da17230869..86a906e0c2 100644 --- a/src/mainboard/google/brya/variants/brask/gpio.c +++ b/src/mainboard/google/brya/variants/brask/gpio.c @@ -26,10 +26,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ |