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authorFelix Held <felix-coreboot@felixheld.de>2021-07-12 22:39:10 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-07-14 02:23:44 +0000
commit2927a66dc9cc1703d937535cb835701f4145ca61 (patch)
treec27363ce76e190424f27b4b21656f1d06c27001e /src
parent7830e3a8363bf804ac72ca3ec4681f79ef9cde46 (diff)
soc/amd/picasso,stoneyridge/mca: factor out mca_check_all_banks
Change-Id: I5496fd27f5c56d35ab95a5e02ea313b5b5536668 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56241 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/picasso/mca.c31
-rw-r--r--src/soc/amd/stoneyridge/mca.c29
2 files changed, 33 insertions, 27 deletions
diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c
index 7561a5609c..973b3b5277 100644
--- a/src/soc/amd/picasso/mca.c
+++ b/src/soc/amd/picasso/mca.c
@@ -164,24 +164,12 @@ static void mca_print_error(unsigned int bank)
printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo);
}
-static void mca_clear_errors(void)
+static void mca_check_all_banks(void)
{
- const unsigned int num_banks = mca_get_bank_count();
- const msr_t msr = {.lo = 0, .hi = 0};
-
- /* Zero all machine check error status registers */
- for (unsigned int i = 0 ; i < num_banks ; i++)
- wrmsr(MCAX_STATUS_MSR(i), msr);
-}
-
-/* Check the Machine Check Architecture Extension registers */
-void check_mca(void)
-{
- unsigned int i;
struct mca_bank_status mci;
const unsigned int num_banks = mca_get_bank_count();
- for (i = 0 ; i < num_banks ; i++) {
+ for (unsigned int i = 0 ; i < num_banks ; i++) {
mci.bank = i;
mci.sts = rdmsr(MCAX_STATUS_MSR(i));
if (mci.sts.hi || mci.sts.lo) {
@@ -191,6 +179,21 @@ void check_mca(void)
build_bert_mca_error(&mci);
}
}
+}
+static void mca_clear_errors(void)
+{
+ const unsigned int num_banks = mca_get_bank_count();
+ const msr_t msr = {.lo = 0, .hi = 0};
+
+ /* Zero all machine check error status registers */
+ for (unsigned int i = 0 ; i < num_banks ; i++)
+ wrmsr(MCAX_STATUS_MSR(i), msr);
+}
+
+/* Check the Machine Check Architecture Extension registers */
+void check_mca(void)
+{
+ mca_check_all_banks();
mca_clear_errors();
}
diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c
index a64b01dd8e..9ba201ea28 100644
--- a/src/soc/amd/stoneyridge/mca.c
+++ b/src/soc/amd/stoneyridge/mca.c
@@ -164,24 +164,13 @@ static void mca_print_error(unsigned int bank)
printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo);
}
-static void mca_clear_errors(void)
-{
- const unsigned int num_banks = mca_get_bank_count();
- const msr_t msr = {.lo = 0, .hi = 0};
-
- /* Zero all machine check error status registers */
- for (unsigned int i = 0 ; i < num_banks ; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
-}
-
-void check_mca(void)
+static void mca_check_all_banks(void)
{
- unsigned int i;
struct mca_bank_status mci;
const unsigned int num_banks = mca_get_bank_count();
if (is_warm_reset()) {
- for (i = 0 ; i < num_banks ; i++) {
+ for (unsigned int i = 0 ; i < num_banks ; i++) {
if (i == 3) /* Reserved in Family 15h */
continue;
@@ -195,6 +184,20 @@ void check_mca(void)
}
}
}
+}
+static void mca_clear_errors(void)
+{
+ const unsigned int num_banks = mca_get_bank_count();
+ const msr_t msr = {.lo = 0, .hi = 0};
+
+ /* Zero all machine check error status registers */
+ for (unsigned int i = 0 ; i < num_banks ; i++)
+ wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+}
+
+void check_mca(void)
+{
+ mca_check_all_banks();
mca_clear_errors();
}