diff options
| author | Tim Van Patten <timvp@google.com> | 2022-08-29 11:36:35 -0600 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-31 19:03:02 +0000 |
| commit | 2873fd277000cbe48348c92b20bce2eaa7212e10 (patch) | |
| tree | 987adbdebebe6d6f16d0b90ef50a55c916b28012 /src | |
| parent | 9e86b71e7936fd17a2b6d2c15ccd81442f21c576 (diff) | |
acpi: Replace EC_ENABLE_AMD_DPTC_SUPPORT with Kconfig value
Compile-time support of DPTC is controlled by
EC_ENABLE_AMD_DPTC_SUPPORT in each variant's ec.h file. This CL removes
EC_ENABLE_AMD_DPTC_SUPPORT and replaces it with the Kconfig value
SOC_AMD_COMMON_BLOCK_ACPI_DPTC.
Each variant's run-time support of DPTC continues to be controlled by
the variant's overridetree.cb "dptc_enable" value.
BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Boot skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ic101e74bab88e20be0cb5aaf66e4349baa1432e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/ec/google/chromeec/acpi/ec.asl | 6 | ||||
| -rw-r--r-- | src/mainboard/google/zork/variants/morphius/include/variant/ec.h | 3 | ||||
| -rw-r--r-- | src/soc/amd/common/block/acpi/Kconfig | 7 | ||||
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 1 |
4 files changed, 11 insertions, 6 deletions
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index b85e1861a0..0914fdda37 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -17,7 +17,7 @@ External (\_SB.DPTF.TCHG, DeviceObj) #endif /* Enable DPTC interface with AMD ALIB */ -#ifdef EC_ENABLE_AMD_DPTC_SUPPORT +#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) External(\_SB.DPTC, MethodObj) #endif @@ -177,7 +177,7 @@ Device (EC0) // Initialize LID switch state Store (LIDS, \LIDS) -#ifdef EC_ENABLE_AMD_DPTC_SUPPORT +#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) /* * Per the device mode (clamshell or tablet) to initialize * the thermal setting on OS startup. @@ -435,7 +435,7 @@ Device (EC0) #ifdef EC_ENABLE_TBMC_DEVICE Notify (TBMC, 0x80) #endif -#ifdef EC_ENABLE_AMD_DPTC_SUPPORT +#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) If (CondRefOf (\_SB.DPTC)) { \_SB.DPTC() } diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h index fbcdf4e0f8..4dc208fd6d 100644 --- a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h +++ b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h @@ -6,9 +6,6 @@ #define SIO_EC_ENABLE_PS2M #define SIO_EC_PS2M_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {12} -/* Enable DPTC support */ -#define EC_ENABLE_AMD_DPTC_SUPPORT - #undef MAINBOARD_EC_S3_WAKE_EVENTS #undef MAINBOARD_EC_S3_DEVICE_EVENTS #define MAINBOARD_EC_S3_WAKE_EVENTS \ diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig index 9c15f21765..46251d6c40 100644 --- a/src/soc/amd/common/block/acpi/Kconfig +++ b/src/soc/amd/common/block/acpi/Kconfig @@ -8,6 +8,13 @@ config SOC_AMD_COMMON_BLOCK_ACPI config SOC_AMD_COMMON_BLOCK_ACPI_ALIB bool +config SOC_AMD_COMMON_BLOCK_ACPI_DPTC + bool + depends on SOC_AMD_COMMON_BLOCK_ACPI_ALIB + help + Selected by mainboards that implement support for ALIB + to enable DPTC. + config SOC_AMD_COMMON_BLOCK_ACPI_CPPC bool diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 30ca13237c..f72f821b5a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPI_ALIB + select SOC_AMD_COMMON_BLOCK_ACPI_DPTC select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPI_IVRS select SOC_AMD_COMMON_BLOCK_AOAC |