diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-28 23:48:56 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-01-11 23:42:19 +0000 |
| commit | 242fd2810c86b82e5aea8f8244c13955dbd8b9db (patch) | |
| tree | 057176f416bde57ac4eb3a57db16ed19f3fdad97 /src | |
| parent | 9dcd1c1173be1cfd5e73d9aca9d6de2353f1b5d9 (diff) | |
cpu/intel/haswell: Allow tuning VR for C-state operations
Apply commit ff0f460e76 (broadwell: Add configuration for tuning VR
for C-state operations) to Haswell, in preparation for unification.
Change-Id: Ib05974e8ed0f73c4f475b90065e8efb14555f9c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46920
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/haswell/chip.h | 29 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/haswell_init.c | 23 |
2 files changed, 50 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 6afed37616..7c2df103a0 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -3,6 +3,33 @@ /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC +#include <stdbool.h> +#include <stdint.h> + +struct cpu_vr_config { + /* + * Minimum voltage for C6/C7 state: + * 0x67 = 1.6V (full swing) + * ... + * 0x79 = 1.7V + * ... + * 0x83 = 1.8V (no swing) + */ + uint8_t cpu_min_vid; + + /* + * Set slow VR ramp rate on C-state exit: + * 0 = Fast VR ramp rate / 2 + * 1 = Fast VR ramp rate / 4 + * 2 = Fast VR ramp rate / 8 + * 3 = Fast VR ramp rate / 16 + */ + uint8_t slow_ramp_rate_set; + + /* Enable slow VR ramp rate */ + bool slow_ramp_rate_enable; +}; + struct cpu_intel_haswell_config { int c1_battery; /* ACPI C1 on Battery Power */ int c2_battery; /* ACPI C2 on Battery Power */ @@ -13,4 +40,6 @@ struct cpu_intel_haswell_config { int c3_acpower; /* ACPI C3 on AC Power */ int tcc_offset; /* TCC Activation Offset */ + + struct cpu_vr_config vr_config; }; diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 369ace9b45..dd1970c033 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -249,8 +249,17 @@ static u32 pcode_mailbox_read(u32 command) static void initialize_vr_config(void) { + struct cpu_vr_config vr_config = { 0 }; msr_t msr; + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + + if (lapic && lapic->chip_info) { + const struct cpu_intel_haswell_config *conf = lapic->chip_info; + + vr_config = conf->vr_config; + } + printk(BIOS_DEBUG, "Initializing VR config.\n"); /* Configure VR_CURRENT_CONFIG. */ @@ -280,13 +289,23 @@ static void initialize_vr_config(void) msr.hi &= ~(1 << (51 - 32)); /* Enable decay mode on C-state entry. */ msr.hi |= (1 << (52 - 32)); + /* Set the slow ramp rate */ if (haswell_is_ult()) { - /* Set the slow ramp rate to be fast ramp rate / 4 */ msr.hi &= ~(0x3 << (53 - 32)); - msr.hi |= (0x01 << (53 - 32)); + /* Configure the C-state exit ramp rate. */ + if (vr_config.slow_ramp_rate_enable) { + /* Configured slow ramp rate. */ + msr.hi |= ((vr_config.slow_ramp_rate_set & 0x3) << (53 - 32)); + /* Set exit ramp rate to slow. */ + msr.hi &= ~(1 << (50 - 32)); + } else { + /* Fast ramp rate / 4. */ + msr.hi |= (1 << (53 - 32)); + } } /* Set MIN_VID (31:24) to allow CPU to have full control. */ msr.lo &= ~0xff000000; + msr.lo |= (vr_config.cpu_min_vid & 0xff) << 24; wrmsr(MSR_VR_MISC_CONFIG, msr); /* Configure VR_MISC_CONFIG2 MSR. */ |