diff options
| author | FrankChu <frank_chu@pegatron.corp-partner.google.com> | 2022-01-14 11:36:35 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-01 11:54:19 +0000 |
| commit | 2302fcf03962c03a6cf80c9978ba8e57ded0e3f6 (patch) | |
| tree | f5f5f712184ec8cb76ceccf19e4425dedc5d4749 /src | |
| parent | 4b4aa0bed6ac261e89e4598b6108097d1e1021c6 (diff) | |
mb/google/dedede/var/galtic: Decrease core display clock to 172.8 MHz
Galtic has a rare stability issue.
The symptom is display black screen while switching to secure mode,
normally it will occurred at the last step of factory side
and it'll follow by some specific SOCs.
Slowing the initial core display clock frequency down to 172.8 MHz
as per Intel recommend for short term solution for Gal series.
The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0
(172.8 MHz) for Galtic.
BUG=b:206557434
BRANCH=dedede
TEST=Build firmware and verify on fail DUTs.
Check the DUTs can boot up in secure mode well.
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ic059ab306f80a6d01f4b0a380a3b767d3245478d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61103
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/dedede/variants/galtic/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb index 150bfe3331..8004736d31 100644 --- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb +++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb @@ -67,6 +67,9 @@ chip soc/intel/jasperlake register "tcc_offset" = "8" # TCC of 97C + # Core Display Clock Frequency selection + register "cd_clock" = "CD_CLOCK_172_8_MHZ" + device domain 0 on device pci 04.0 on # Default DPTF Policy for all Dedede boards if not overridden |