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authorTarun Tuli <taruntuli@google.com>2022-09-02 15:20:22 -0400
committerMartin L Roth <gaumless@gmail.com>2022-09-04 18:55:07 +0000
commit218fac11087d3c1ad69327e4e926ab7ba5a6465f (patch)
treef3fe62644a2013c3900fa3895c9711b889106a8e /src
parent0dd3cf4534c4ab9497b5c7b3af5e0ed8b9e919df (diff)
mb/google/rex: Correct GPSI0 muxing for pads requiring NF8
GSPI0 pads required muxing to NF8. Support for extended native functions was added in commit b6c32d7fe4ea98ba8b3a10cb5ce46448801855b8 BUG=b:244610269 TEST=build and booted on Rex Change-Id: Iab4e0bc6890cd8e976c513fe87dda0da9b5f2ee0 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/rex/variants/rex0/gpio.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c
index 8f4ea6c543..23a0f5b52a 100644
--- a/src/mainboard/google/rex/variants/rex0/gpio.c
+++ b/src/mainboard/google/rex/variants/rex0/gpio.c
@@ -258,15 +258,15 @@ static const struct pad_config gpio_table_id0[] = {
/* GPP_F13 : GSPI1_SOC_DI_FPMCU_DO_LS */
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF5),
/* GPP_F14 : GSPI_SOC_DO_TCHSCR_DI */
- PAD_NC(GPP_F14, NONE),
+ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
/* GPP_F15 : [] ==> GSPI_SOC_DI_TCHSCR_DO */
- PAD_NC(GPP_F15, NONE),
+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
/* GPP_F16 : [] ==> GSPI_SOC_TCHSCR_CLK */
- PAD_NC(GPP_F16, NONE),
+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
/* GPP_F17 : [] ==> GSPI1_SOC_CS_L */
PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5),
/* GPP_F18 : [] ==> GSPI_SOC_TCHSCR_CS_L */
- PAD_NC(GPP_F18, NONE),
+ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
/* GPP_F19 : [] ==> GPP_F19_STRAP */
PAD_NC(GPP_F19, NONE),
/* GPP_F20 : [] ==> GPP_F20_STRAP */