soc/intel/cmn/graphics: Implement API for IGD to join the MBUS

This patch implements `.final` hooks for the IGD device to perform the
required operations before handing the control to the payload or OS.

The MBUS (Memory Bus) is a high-speed interface that connects the
graphics controller to the system memory. It provides a dedicated data
path for graphics data, which helps to improve graphics performance.

The MBUS is a key technology that helps to make the Intel i915 driver
powerful and versatile graphics drivers available. It provides the
high-speed data transfer capabilities that are essential for smooth
and responsive graphics performance.

Enable this config to ensure that the Intel GFX controller joins the
MBUS before the i915 driver is loaded. This is necessary to prevent
the i915 driver from re-initializing the display if the firmware has
already initialized it. Without this config, the i915 driver will
initialize the display to bring up the login screen although the
firmware has initialized the display using the GFX MMIO registers and
framebuffer.

Kernel graphics driver can avoid redundant display init by firmware,
which can optimize boot time by ~15ms-30ms.

Ensures hashing mode is 1x4 to enable a single pipe between Pipe A or B.
Typically, internal display is on Pipe-A, so 1x4 restricts MBUS joining
to internal display alone.

BUG=b:284799726
TEST=Able to build and boot google/rex

Change-Id: I60ae76dc783383e027e66edbcdeeb535472caeb1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78385
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 41 insertions, 1 deletions

diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig
index d586fd8ab8..30e4f8e800 100644
--- a/src/soc/intel/common/block/graphics/Kconfig
+++ b/src/soc/intel/common/block/graphics/Kconfig
@@ -37,4 +37,24 @@ config SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO
 	  Ignore BAR0(offset 0x10)'s pre-fetchable attribute to use non-prefetchable
 	  MMIO to fix OS display driver failure.
 
+config SOC_INTEL_GFX_MBUS_JOIN
+	bool
+	help
+	  The MBUS (Memory Bus) is a high-speed interface that connects the graphics
+	  controller to the system memory. It provides a dedicated data path for graphics
+	  data, which helps to improve graphics performance.
+
+	  The MBUS is a key technology that helps to make the Intel i915 driver powerful
+	  and versatile graphics drivers available. It provides the high-speed data transfer
+	  capabilities that are essential for smooth and responsive graphics performance.
+
+	  Enable this config to ensure that the Intel GFX controller joins the MBUS before the
+	  i915 driver is loaded. This is necessary to prevent the i915 driver from re-initializing
+	  the display if the firmware has already initialized it. Without this config, the i915
+	  driver will initialize the display to bring up the login screen although the firmware
+	  has initialized the display using the GFX MMIO registers and framebuffer.
+
+	  When enabled, saves 75ms-80ms of the boot time by avoiding redundent display
+	  initialization by kernel graphics driver (i.e., i915_gfx).
+
 endif
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 9d541d0208..4bec7a4cc6 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -16,6 +16,11 @@
 #include <soc/pci_devs.h>
 #include <types.h>
 
+#define GFX_MBUS_CTL		0x4438C
+#define GFX_MBUS_JOIN		BIT(31)
+#define GFX_MBUS_HASHING_MODE	BIT(30)
+#define GFX_MBUS_JOIN_PIPE_SEL	(BIT(28) | BIT(27) | BIT(26))
+
 /* SoC Overrides */
 __weak void graphics_soc_panel_init(struct device *dev)
 {
@@ -256,12 +261,27 @@ static void graphics_dev_read_resources(struct device *dev)
 	}
 }
 
+static void graphics_dev_final(struct device *dev)
+{
+	pci_dev_request_bus_master(dev);
+
+	if (CONFIG(SOC_INTEL_GFX_MBUS_JOIN)) {
+		uint32_t hashing_mode = 0;  /* 2x2 */
+		uint32_t pipe_select = 0; /* None */
+		if (!get_external_display_status()) {
+			hashing_mode = GFX_MBUS_HASHING_MODE; /* 1x4 */
+			pipe_select = GFX_MBUS_JOIN_PIPE_SEL; /* Pipe-A */
+		}
+		graphics_gtt_rmw(GFX_MBUS_CTL, (uint32_t)(~pipe_select), GFX_MBUS_JOIN | hashing_mode);
+	}
+}
+
 const struct device_operations graphics_ops = {
 	.read_resources		= graphics_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= gma_init,
-	.final			= pci_dev_request_bus_master,
+	.final			= graphics_dev_final,
 	.ops_pci		= &pci_dev_ops_pci,
 #if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_fill_ssdt		= gma_generate_ssdt,