AGESA, binaryPI: implement C bootblock

Modify CAR setup to work in bootblock. Provide bootblock C file with
necessary C bootblock functions. Additionally chache the ROM and set
the MMCONF base before jumping to bootblock main.

Change-Id: I29916a96f490ff717c69dc7cd565d74a83dbfb0d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36914
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 106 insertions, 5 deletions

diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 5e1ff1d6c9..2c8f9c5e37 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -49,6 +49,14 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x10000
 
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x4000
+
+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0x8000
+
 config ENABLE_MRC_CACHE
 	bool "Use cached memory configuration"
 	default n
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index 728c7b1ce7..c534b4d6e8 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -48,6 +48,14 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x10000
 
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x4000
+
+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0x8000
+
 endif # CPU_AMD_PI
 
 source "src/cpu/amd/pi/00630F01/Kconfig"
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index 9454f8f00a..0d114782e1 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -1,6 +1,7 @@
 ramstage-y += lapic.c
 ramstage-y += lapic_cpu_init.c
 ramstage-$(CONFIG_SMP) += secondary.S
+bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
 romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
 postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc
index dfb385da80..3c3c4fc621 100644
--- a/src/drivers/amd/agesa/Makefile.inc
+++ b/src/drivers/amd/agesa/Makefile.inc
@@ -19,7 +19,13 @@ romstage-y += state_machine.c
 
 ramstage-y += state_machine.c
 
+ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
+bootblock-y += bootblock.c
+bootblock-y += cache_as_ram.S
+else
 cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S
+endif
+
 postcar-y += exit_car.S
 
 romstage-y += def_callouts.c
diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c
new file mode 100644
index 0000000000..3763b98a3a
--- /dev/null
+++ b/src/drivers/amd/agesa/bootblock.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <halt.h>
+#include <timestamp.h>
+#include <amdblocks/amd_pci_mmconf.h>
+#include <amdblocks/biosram.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
+
+#define EARLY_VMTRR_FLASH 6
+
+static void set_early_mtrrs(void)
+{
+	/* Cache the ROM to speed up booting */
+	set_var_mtrr(EARLY_VMTRR_FLASH, OPTIMAL_CACHE_ROM_BASE,
+		     OPTIMAL_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
+}
+
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+	enable_pci_mmconf();
+	set_early_mtrrs();
+
+	bootblock_main_with_basetime(base_timestamp);
+}
+
+asmlinkage void ap_bootblock_c_entry(void)
+{
+	enable_pci_mmconf();
+	set_early_mtrrs();
+
+	void (*ap_romstage_entry)(void) = get_ap_entry_ptr();
+	ap_romstage_entry(); /* execution does not return */
+	halt();
+}
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index 4417e64595..1034992e17 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -27,9 +27,17 @@
 
 .code32
 .globl _cache_as_ram_setup, _cache_as_ram_setup_end
+.global bootblock_pre_c_entry
 
 _cache_as_ram_setup:
 
+/*
+ * on entry:
+ *   mm0: BIST (ignored)
+ *   mm2_mm1: timestamp at bootblock_protected_mode_entry
+ */
+bootblock_pre_c_entry:
+
 	post_code(0xa0)
 
 	AMD_ENABLE_STACK
@@ -51,8 +59,10 @@ _cache_as_ram_setup:
 	and	$0xfffffff0, %esp
 	sub	$8, %esp
 
-	pushl	$0		/* tsc[63:32] */
-	pushl	$0		/* tsc[31:0] */
+	movd	%mm2, %eax
+	pushl	%eax		/* tsc[63:32] */
+	movd	%mm1, %eax
+	pushl	%eax		/* tsc[31:0] */
 
 	post_code(0xa2)
 
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index 48a81c57df..dbf8bd6070 100644
--- a/src/drivers/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
@@ -11,6 +11,7 @@
  * GNU General Public License for more details.
  */
 
+#include <amdblocks/biosram.h>
 #include <arch/acpi.h>
 #include <arch/cpu.h>
 #include <arch/romstage.h>
@@ -26,6 +27,8 @@
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
+void __weak board_BeforeAgesa(struct sysinfo *cb) { }
+
 void __weak platform_once(struct sysinfo *cb)
 {
 	board_BeforeAgesa(cb);
@@ -39,6 +42,11 @@ static void fill_sysinfo(struct sysinfo *cb)
 	agesa_set_interface(cb);
 }
 
+/* APs will enter directly here from bootblock, bypassing verstage
+ * and potential fallback / normal bootflow detection.
+ */
+static void ap_romstage_main(void);
+
 static void romstage_main(void)
 {
 	struct postcar_frame pcf;
@@ -48,13 +56,15 @@ static void romstage_main(void)
 	int cbmem_initted = 0;
 
 	/* Enable PCI MMIO configuration. */
-	amd_initmmio();
+	if (CONFIG(ROMCC_BOOTBLOCK))
+		amd_initmmio();
 
 	fill_sysinfo(cb);
 
 	if (initial_apic_id == 0) {
 
-		timestamp_init(timestamp_get());
+		if (CONFIG(ROMCC_BOOTBLOCK))
+			timestamp_init(timestamp_get());
 		timestamp_add_now(TS_START_ROMSTAGE);
 
 		platform_once(cb);
@@ -65,6 +75,9 @@ static void romstage_main(void)
 	printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n",
 		initial_apic_id, cpuid_eax(1));
 
+	if (!CONFIG(ROMCC_BOOTBLOCK))
+		set_ap_entry_ptr(ap_romstage_main);
+
 	agesa_execute_state(cb, AMD_INIT_RESET);
 
 	agesa_execute_state(cb, AMD_INIT_EARLY);
@@ -105,7 +118,8 @@ static void ap_romstage_main(void)
 	struct sysinfo *cb = &romstage_state;
 
 	/* Enable PCI MMIO configuration. */
-	amd_initmmio();
+	if (CONFIG(ROMCC_BOOTBLOCK))
+		amd_initmmio();
 
 	fill_sysinfo(cb);
 
@@ -117,6 +131,7 @@ static void ap_romstage_main(void)
 	halt();
 }
 
+#if CONFIG(ROMCC_BOOTBLOCK)
 /* This wrapper enables easy transition away from ROMCC_BOOTBLOCK
  * keeping changes in cache_as_ram.S easy to manage.
  */
@@ -129,3 +144,9 @@ asmlinkage void ap_bootblock_c_entry(void)
 {
 	ap_romstage_main();
 }
+#else
+asmlinkage void car_stage_entry(void)
+{
+	romstage_main();
+}
+#endif