diff options
| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-27 14:02:36 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-27 23:48:35 +0200 |
| commit | 13e4182119bcfcf09bdd9fa2b0cc5d09cd3550c2 (patch) | |
| tree | 286cfd31710cf8817b1969d4552ea0fa778a66b4 /src | |
| parent | d0398f135f61c8e9c4d50655d08a35d2816690fb (diff) | |
kbuild: automatically include southbridges
This change switches all southbridge vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in southbridge/Makefile.inc or in
southbridge/<vendor>/Makefile.inc.
In order to be able to drop southbridge/amd/Makefile.inc, some
scattered source files had to be moved to a southbridge/amd/common
directory, in accordance to what we are doing on other architectures
already.
This means, vendor and southbridge directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).
Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9796
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
76 files changed, 209 insertions, 128 deletions
diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c index e73a3e81d2..079abdbc4c 100644 --- a/src/mainboard/amd/lamar/mainboard.c +++ b/src/mainboard/amd/lamar/mainboard.c @@ -32,7 +32,7 @@ #include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <southbridge/amd/pi/hudson/pci_devs.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c index 8b5b5ea7aa..d29127c560 100644 --- a/src/mainboard/amd/lamar/mptable.c +++ b/src/mainboard/amd/lamar/mptable.c @@ -27,7 +27,7 @@ #include <cpu/amd/amdfam15.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> #include <arch/ioapic.h> #include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 58ac9833ac..9479b2b104 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -24,7 +24,7 @@ #include <arch/io.h> #include <cpu/x86/msr.h> #include <device/pci_def.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/cimx_util.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 0cf57bdcce..b5f65355a8 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -27,7 +27,7 @@ #include <stdint.h> #include <cpu/amd/amdfam14.h> #include <SBPLATFORM.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> #include <arch/ioapic.h> diff --git a/src/mainboard/biostar/am1ml/mainboard.c b/src/mainboard/biostar/am1ml/mainboard.c index fed21ba06b..d402150302 100644 --- a/src/mainboard/biostar/am1ml/mainboard.c +++ b/src/mainboard/biostar/am1ml/mainboard.c @@ -33,7 +33,7 @@ #include <northbridge/amd/agesa/agesawrapper.h> #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c index b2851ff0b3..f80b9740f6 100644 --- a/src/mainboard/biostar/am1ml/mptable.c +++ b/src/mainboard/biostar/am1ml/mptable.c @@ -27,7 +27,7 @@ #include <cpu/amd/amdfam16.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> static void *smp_write_config_table(void *v) diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c index c4a20c64d1..a95e2ee350 100644 --- a/src/mainboard/gizmosphere/gizmo2/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo2/mainboard.c @@ -29,7 +29,7 @@ #include <arch/acpi.h> #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <cpu/amd/agesa/s3_resume.h> diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c index 192b0c07f9..c61952fe58 100644 --- a/src/mainboard/gizmosphere/gizmo2/mptable.c +++ b/src/mainboard/gizmosphere/gizmo2/mptable.c @@ -27,7 +27,7 @@ #include <cpu/amd/amdfam16.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> static void *smp_write_config_table(void *v) diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c index adb70930c8..71193bbcea 100644 --- a/src/mainboard/hp/abm/mainboard.c +++ b/src/mainboard/hp/abm/mainboard.c @@ -26,7 +26,7 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <cpu/amd/agesa/s3_resume.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index d67e072b8a..2dc92e7a93 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -30,7 +30,7 @@ #include <device/pci.h> #include <device/pci_def.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <southbridge/amd/cimx/cimx_util.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index cc73c835b7..5d02877efd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -30,7 +30,7 @@ #include <stdint.h> #include <string.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 1ba0e2345a..3b8541cae1 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -24,7 +24,7 @@ #include <arch/io.h> #include <cpu/x86/msr.h> #include <device/pci_def.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/cimx_util.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c index 03fa9f37d6..95a00afff4 100644 --- a/src/mainboard/pcengines/apu1/mptable.c +++ b/src/mainboard/pcengines/apu1/mptable.c @@ -27,7 +27,7 @@ #include <stdint.h> #include <cpu/amd/amdfam14.h> #include <SBPLATFORM.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> #include <arch/ioapic.h> diff --git a/src/southbridge/Makefile.inc b/src/southbridge/Makefile.inc deleted file mode 100644 index 106752b0b2..0000000000 --- a/src/southbridge/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -subdirs-y += amd -subdirs-y += broadcom -subdirs-y += dmp -subdirs-y += intel -subdirs-y += nvidia -subdirs-y += rdc -subdirs-y += ricoh -subdirs-y += sis -subdirs-y += ti -subdirs-y += via diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc deleted file mode 100644 index cfb89d5a1d..0000000000 --- a/src/southbridge/amd/Makefile.inc +++ /dev/null @@ -1,27 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8131) += amd8131 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8132) += amd8132 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8151) += amd8151 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS690) += rs690 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB600) += sb600 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS780) += rs780 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB700) += sb700 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB800) += sb800 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SR5650) += sr5650 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += agesa -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += pi -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += pi - -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc index fdd5d8047a..89d41b4a97 100644 --- a/src/southbridge/amd/agesa/Makefile.inc +++ b/src/southbridge/amd/agesa/Makefile.inc @@ -16,5 +16,6 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 5858cd2ef7..cf1626d252 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include "hudson.h" -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <bootstate.h> diff --git a/src/southbridge/amd/amd8111/Makefile.inc b/src/southbridge/amd/amd8111/Makefile.inc index c5b2688e0d..4c9ebaed88 100644 --- a/src/southbridge/amd/amd8111/Makefile.inc +++ b/src/southbridge/amd/amd8111/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8111),y) + ramstage-y += amd8111.c ramstage-y += usb.c ramstage-y += lpc.c @@ -9,3 +11,5 @@ ramstage-y += nic.c ramstage-y += pci.c ramstage-y += smbus.c ramstage-y += reset.c + +endif diff --git a/src/southbridge/amd/amd8131/Makefile.inc b/src/southbridge/amd/amd8131/Makefile.inc index ce96c9717b..8ec269157c 100644 --- a/src/southbridge/amd/amd8131/Makefile.inc +++ b/src/southbridge/amd/amd8131/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8131),y) + ramstage-y += bridge.c + +endif diff --git a/src/southbridge/amd/amd8132/Makefile.inc b/src/southbridge/amd/amd8132/Makefile.inc index ce96c9717b..75dce39f54 100644 --- a/src/southbridge/amd/amd8132/Makefile.inc +++ b/src/southbridge/amd/amd8132/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y) + ramstage-y += bridge.c + +endif diff --git a/src/southbridge/amd/amd8151/Makefile.inc b/src/southbridge/amd/amd8151/Makefile.inc index dcb3c73543..07edf58085 100644 --- a/src/southbridge/amd/amd8151/Makefile.inc +++ b/src/southbridge/amd/amd8151/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8151),y) + ramstage-y += agp3.c + +endif diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index aacfc5844b..0754469b4e 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -16,10 +16,15 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 -romstage-y += cimx_util.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c -ramstage-y += cimx_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index f4a7aa341a..ffa3290c8c 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -38,7 +38,7 @@ #include "sb_cimx.h" /* AMD CIMX wrapper entries */ #include "smbus.h" #include "fan.h" -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> /*implement in mainboard.c*/ void set_pcie_reset(void); diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc new file mode 100644 index 0000000000..1f847cd0bb --- /dev/null +++ b/src/southbridge/amd/common/Makefile.inc @@ -0,0 +1,7 @@ +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c diff --git a/src/southbridge/amd/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index 9f2cc5c1ee..9f2cc5c1ee 100644 --- a/src/southbridge/amd/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c diff --git a/src/southbridge/amd/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h index 1d1e52baaf..1d1e52baaf 100644 --- a/src/southbridge/amd/amd_pci_util.h +++ b/src/southbridge/amd/common/amd_pci_util.h diff --git a/src/southbridge/amd/cs5535/Makefile.inc b/src/southbridge/amd/cs5535/Makefile.inc index 6f65e2e30d..3785cd4002 100644 --- a/src/southbridge/amd/cs5535/Makefile.inc +++ b/src/southbridge/amd/cs5535/Makefile.inc @@ -1,4 +1,8 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5535),y) + ramstage-y += cs5535.c #ramstage-y += pci.c #ramstage-y += ide.c ramstage-y += chipsetinit.c + +endif diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc index f36dcc54a6..2da076e14a 100644 --- a/src/southbridge/amd/cs5536/Makefile.inc +++ b/src/southbridge/amd/cs5536/Makefile.inc @@ -17,8 +17,12 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y) + ramstage-y += cs5536.c ramstage-y += ide.c ramstage-y += pirq.c ramstage-y += smbus.c -romstage-y += smbus.c
\ No newline at end of file +romstage-y += smbus.c + +endif diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index 70e2c18854..5e71b4b242 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include "hudson.h" -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <bootstate.h> static void pci_init(struct device *dev) diff --git a/src/southbridge/amd/rs690/Makefile.inc b/src/southbridge/amd/rs690/Makefile.inc index e0cf927812..c80ed9b611 100644 --- a/src/southbridge/amd/rs690/Makefile.inc +++ b/src/southbridge/amd/rs690/Makefile.inc @@ -1,5 +1,9 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS690),y) + ramstage-y += rs690.c ramstage-y += cmn.c ramstage-y += pcie.c ramstage-y += ht.c ramstage-y += gfx.c + +endif diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc index bf51d83e8f..1a8a17acac 100644 --- a/src/southbridge/amd/rs780/Makefile.inc +++ b/src/southbridge/amd/rs780/Makefile.inc @@ -1,5 +1,9 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS790),y) + ramstage-y += rs780.c ramstage-y += cmn.c ramstage-y += pcie.c ramstage-y += ht.c ramstage-y += gfx.c + +endif diff --git a/src/southbridge/amd/sb600/Makefile.inc b/src/southbridge/amd/sb600/Makefile.inc index 37fe57df1a..cd5bb6166d 100644 --- a/src/southbridge/amd/sb600/Makefile.inc +++ b/src/southbridge/amd/sb600/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB600),y) + ramstage-y += sb600.c ramstage-y += usb.c ramstage-y += lpc.c @@ -10,3 +12,5 @@ ramstage-y += pci.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c + +endif diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc index 6e772fe5d1..5ec84312a3 100644 --- a/src/southbridge/amd/sb700/Makefile.inc +++ b/src/southbridge/amd/sb700/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB700),y) + ramstage-y += sb700.c ramstage-y += usb.c ramstage-y += lpc.c @@ -15,3 +17,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c romstage-y += smbus.c + +endif diff --git a/src/southbridge/amd/sb800/Makefile.inc b/src/southbridge/amd/sb800/Makefile.inc index d665af4639..fca4a984cb 100644 --- a/src/southbridge/amd/sb800/Makefile.inc +++ b/src/southbridge/amd/sb800/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB800),y) + ramstage-y += sb800.c ramstage-y += usb.c ramstage-y += lpc.c @@ -11,3 +13,5 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c + +endif diff --git a/src/southbridge/amd/sr5650/Makefile.inc b/src/southbridge/amd/sr5650/Makefile.inc index 3c17be07c0..f695a112a6 100644 --- a/src/southbridge/amd/sr5650/Makefile.inc +++ b/src/southbridge/amd/sr5650/Makefile.inc @@ -1,5 +1,9 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SR5650),y) + ramstage-y += sr5650.c ramstage-y += pcie.c ramstage-y += ht.c romstage-y += early_setup.c + +endif diff --git a/src/southbridge/broadcom/Makefile.inc b/src/southbridge/broadcom/Makefile.inc deleted file mode 100644 index c9de93d8bc..0000000000 --- a/src/southbridge/broadcom/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM21000) += bcm21000 -subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5780) += bcm5780 -subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5785) += bcm5785 diff --git a/src/southbridge/broadcom/bcm21000/Makefile.inc b/src/southbridge/broadcom/bcm21000/Makefile.inc index f85aeb1363..d298c8e008 100644 --- a/src/southbridge/broadcom/bcm21000/Makefile.inc +++ b/src/southbridge/broadcom/bcm21000/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM21000),y) + ramstage-y += pcie.c + +endif diff --git a/src/southbridge/broadcom/bcm5780/Makefile.inc b/src/southbridge/broadcom/bcm5780/Makefile.inc index 4eb834a74d..d4f83ed4ab 100644 --- a/src/southbridge/broadcom/bcm5780/Makefile.inc +++ b/src/southbridge/broadcom/bcm5780/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5870),y) + ramstage-y += nic.c ramstage-y += pcix.c ramstage-y += pcie.c + +endif diff --git a/src/southbridge/broadcom/bcm5785/Makefile.inc b/src/southbridge/broadcom/bcm5785/Makefile.inc index b8427c4ff6..70fba1f218 100644 --- a/src/southbridge/broadcom/bcm5785/Makefile.inc +++ b/src/southbridge/broadcom/bcm5785/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5785),y) + ramstage-y += bcm5785.c ramstage-y += usb.c ramstage-y += lpc.c @@ -5,3 +7,5 @@ ramstage-y += sb_pci_main.c ramstage-y += ide.c ramstage-y += sata.c ramstage-y += reset.c + +endif diff --git a/src/southbridge/dmp/Makefile.inc b/src/southbridge/dmp/Makefile.inc deleted file mode 100644 index a94e935b80..0000000000 --- a/src/southbridge/dmp/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 DMP Electronics Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-$(CONFIG_SOUTHBRIDGE_DMP_VORTEX86EX) += vortex86ex diff --git a/src/southbridge/dmp/vortex86ex/Makefile.inc b/src/southbridge/dmp/vortex86ex/Makefile.inc index 5471faa6da..968930bdbf 100644 --- a/src/southbridge/dmp/vortex86ex/Makefile.inc +++ b/src/southbridge/dmp/vortex86ex/Makefile.inc @@ -17,7 +17,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_DMP_VORTEX86EX),y) + ramstage-y += southbridge.c ramstage-y += hard_reset.c ramstage-y += ide_sd_sata.c ramstage-y += audio.c + +endif diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc deleted file mode 100644 index dd20d46b06..0000000000 --- a/src/southbridge/intel/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON) += common -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_ESB6300) += esb6300 -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I3100) += i3100 -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801AX) += i82801ax -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801BX) += i82801bx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CX) += i82801cx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) += i82801dx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801EX) += i82801ex -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) += i82801ix -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870 -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_SCH) += sch -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += bd82x6x -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += bd82x6x -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK) += ibexpeak -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT) += lynxpoint -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X) += fsp_bd82x6x -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_rangeley diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 83de051d51..234c009716 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -107,3 +109,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) endif PHONY += bd82x6x_add_me + +endif diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 4374ebcb43..5c613ebb4c 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -17,5 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) + romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c + +endif diff --git a/src/southbridge/intel/esb6300/Makefile.inc b/src/southbridge/intel/esb6300/Makefile.inc index bb70fdcc62..fba8c2310b 100644 --- a/src/southbridge/intel/esb6300/Makefile.inc +++ b/src/southbridge/intel/esb6300/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_ESB6300),y) + ramstage-y += esb6300.c ramstage-y += reset.c ramstage-y += uhci.c @@ -10,3 +12,5 @@ ramstage-y += pci.c ramstage-y += pic.c ramstage-y += bridge1c.c ramstage-y += ac97.c + +endif diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc index 208611b716..1bfed232d8 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc +++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -71,3 +73,5 @@ endif PHONY += bd82x6x_add_me CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x + +endif diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc index 48ac522ddd..1d3305288b 100644 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -48,3 +50,5 @@ rangeley_add_descriptor: $(obj)/coreboot.pre $(IFDTOOL) endif PHONY += rangeley_add_descriptor + +endif diff --git a/src/southbridge/intel/i3100/Makefile.inc b/src/southbridge/intel/i3100/Makefile.inc index dc3d0395e9..bcc6d06171 100644 --- a/src/southbridge/intel/i3100/Makefile.inc +++ b/src/southbridge/intel/i3100/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I3100),y) + ramstage-y += i3100.c ramstage-y += uhci.c ramstage-y += lpc.c @@ -8,3 +10,5 @@ ramstage-y += pci.c ramstage-y += ioapic.c ramstage-y += reset.c ramstage-y += pciexp_portb.c + +endif diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index 0aae455980..0ab2531e70 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y) + ramstage-y += i82371eb.c ramstage-y += isa.c ramstage-y += ide.c @@ -30,3 +32,5 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c romstage-y += early_pm.c romstage-y += early_smbus.c + +endif diff --git a/src/southbridge/intel/i82801ax/Makefile.inc b/src/southbridge/intel/i82801ax/Makefile.inc index aeb1e54901..48eadf396d 100644 --- a/src/southbridge/intel/i82801ax/Makefile.inc +++ b/src/southbridge/intel/i82801ax/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801AX),y) + ramstage-y += i82801ax.c ramstage-y += ac97.c ramstage-y += ide.c @@ -30,3 +32,5 @@ ramstage-y += reset.c ramstage-y += watchdog.c romstage-y += early_smbus.c + +endif diff --git a/src/southbridge/intel/i82801bx/Makefile.inc b/src/southbridge/intel/i82801bx/Makefile.inc index f070f05891..44a2ac8836 100644 --- a/src/southbridge/intel/i82801bx/Makefile.inc +++ b/src/southbridge/intel/i82801bx/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801BX),y) + ramstage-y += i82801bx.c ramstage-y += ac97.c ramstage-y += ide.c @@ -31,3 +33,5 @@ ramstage-y += reset.c ramstage-y += watchdog.c romstage-y += early_smbus.c + +endif diff --git a/src/southbridge/intel/i82801cx/Makefile.inc b/src/southbridge/intel/i82801cx/Makefile.inc index c375476d47..ab95982a04 100644 --- a/src/southbridge/intel/i82801cx/Makefile.inc +++ b/src/southbridge/intel/i82801cx/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801CX),y) + ramstage-y += i82801cx.c ramstage-y += usb.c ramstage-y += lpc.c @@ -6,3 +8,5 @@ ramstage-y += ac97.c #ramstage-y += nic.c ramstage-y += pci.c ramstage-y += reset.c + +endif diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index e412ef9089..d10383cc5a 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -19,6 +19,8 @@ ## MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y) + ramstage-y += i82801dx.c ramstage-y += ac97.c ramstage-y += ide.c @@ -33,3 +35,5 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c + +endif diff --git a/src/southbridge/intel/i82801ex/Makefile.inc b/src/southbridge/intel/i82801ex/Makefile.inc index fb76a98453..240eaf0517 100644 --- a/src/southbridge/intel/i82801ex/Makefile.inc +++ b/src/southbridge/intel/i82801ex/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801EX),y) + ramstage-y += i82801ex.c ramstage-y += uhci.c ramstage-y += lpc.c @@ -9,3 +11,5 @@ ramstage-y += pci.c ramstage-y += ac97.c ramstage-y += watchdog.c ramstage-y += reset.c + +endif diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 6e4d42e519..fa1721f26f 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) + ramstage-y += i82801gx.c ramstage-y += ac97.c ramstage-y += azalia.c @@ -39,3 +41,5 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c early_lpc.c + +endif diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index a6580c4208..19f5bb432a 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801IX),y) + ramstage-y += i82801ix.c ramstage-y += pci.c ramstage-y += lpc.c @@ -40,3 +42,5 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_init.c romstage-y += early_smbus.c romstage-y += dmi_setup.c + +endif diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc index 190aa4f1e9..790bd01513 100644 --- a/src/southbridge/intel/i82870/Makefile.inc +++ b/src/southbridge/intel/i82870/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y) + ramstage-y += ioapic.c ramstage-y += pcibridge.c #ramstage-y += pci_parity.c + +endif diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 393655ddbe..f09db1a03e 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -100,3 +102,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) endif PHONY += bd82x6x_add_me + +endif diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 3b7663ea04..df68db2473 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -104,3 +106,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) endif PHONY += lynxpoint_add_me + +endif diff --git a/src/southbridge/intel/sch/Makefile.inc b/src/southbridge/intel/sch/Makefile.inc index 0bdd4759e3..bfdbe04266 100644 --- a/src/southbridge/intel/sch/Makefile.inc +++ b/src/southbridge/intel/sch/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_SCH),y) + ramstage-y += south.c ramstage-y += audio.c ramstage-y += lpc.c @@ -39,3 +41,5 @@ cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin cmc.bin-file := $(call strip_quotes,$(CONFIG_CMC_FILE)) cmc.bin-type := raw cmc.bin-position := 0xfffd0000 + +endif diff --git a/src/southbridge/nvidia/Makefile.inc b/src/southbridge/nvidia/Makefile.inc deleted file mode 100644 index 13bf3e4560..0000000000 --- a/src/southbridge/nvidia/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) += ck804 -subdirs-$(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55) += mcp55 diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index c88da3994d..de1162a656 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_CK804),y) + ramstage-y += ck804.c ramstage-y += usb.c ramstage-y += lpc.c @@ -21,3 +23,5 @@ romstage-y += early_smbus.c chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc bootblock-y += romstrap.ld + +endif diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index e2f8553939..3e24f1c293 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y) + ramstage-y += mcp55.c ramstage-y += azalia.c ramstage-y += ht.c @@ -20,3 +22,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc bootblock-y += romstrap.ld + +endif diff --git a/src/southbridge/rdc/Makefile.inc b/src/southbridge/rdc/Makefile.inc deleted file mode 100644 index 34f3efdfec..0000000000 --- a/src/southbridge/rdc/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_RDC_R8610) += r8610 diff --git a/src/southbridge/rdc/r8610/Makefile.inc b/src/southbridge/rdc/r8610/Makefile.inc index 3484c95eca..c6866bc989 100644 --- a/src/southbridge/rdc/r8610/Makefile.inc +++ b/src/southbridge/rdc/r8610/Makefile.inc @@ -17,4 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_RDC_R8610),y) + ramstage-y += r8610.c + +endif diff --git a/src/southbridge/ricoh/Makefile.inc b/src/southbridge/ricoh/Makefile.inc deleted file mode 100644 index 3969392d44..0000000000 --- a/src/southbridge/ricoh/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_RICOH_RL5C476) += rl5c476 diff --git a/src/southbridge/ricoh/rl5c476/Makefile.inc b/src/southbridge/ricoh/rl5c476/Makefile.inc index 315670693b..3fa232f1f8 100644 --- a/src/southbridge/ricoh/rl5c476/Makefile.inc +++ b/src/southbridge/ricoh/rl5c476/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_RICOH_RL5C476),y) + ramstage-y += rl5c476.c + +endif diff --git a/src/southbridge/sis/Makefile.inc b/src/southbridge/sis/Makefile.inc deleted file mode 100644 index 45332ca295..0000000000 --- a/src/southbridge/sis/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_SIS_SIS966) += sis966 diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index 5cf5954992..71fff02685 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_SIS_SIS966),y) + ramstage-y += sis761.c ramstage-y += sis966.c ramstage-y += lpc.c @@ -15,3 +17,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc bootblock-y += romstrap.ld + +endif diff --git a/src/southbridge/ti/Makefile.inc b/src/southbridge/ti/Makefile.inc deleted file mode 100644 index 2bd00e700a..0000000000 --- a/src/southbridge/ti/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI7420) += pci7420 -subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCIXX12) += pcixx12 -subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x diff --git a/src/southbridge/ti/pci1x2x/Makefile.inc b/src/southbridge/ti/pci1x2x/Makefile.inc index 7c0e4aac0e..4f2a3d3ec9 100644 --- a/src/southbridge/ti/pci1x2x/Makefile.inc +++ b/src/southbridge/ti/pci1x2x/Makefile.inc @@ -1 +1,5 @@ -ramstage-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x.c +ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI1X2X),y) + +ramstage-y += pci1x2x.c + +endif diff --git a/src/southbridge/ti/pci7420/Makefile.inc b/src/southbridge/ti/pci7420/Makefile.inc index d919258374..66cfa90894 100644 --- a/src/southbridge/ti/pci7420/Makefile.inc +++ b/src/southbridge/ti/pci7420/Makefile.inc @@ -17,5 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI7420),y) + ramstage-y += cardbus.c ramstage-y += firewire.c + +endif diff --git a/src/southbridge/ti/pcixx12/Makefile.inc b/src/southbridge/ti/pcixx12/Makefile.inc index bdd2cf37ec..6ab571b3d1 100644 --- a/src/southbridge/ti/pcixx12/Makefile.inc +++ b/src/southbridge/ti/pcixx12/Makefile.inc @@ -17,4 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCIXX12),y) + ramstage-y += pcixx12.c + +endif diff --git a/src/southbridge/via/Makefile.inc b/src/southbridge/via/Makefile.inc deleted file mode 100644 index db19438005..0000000000 --- a/src/southbridge/via/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890 -subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8237R) += vt8237r diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index 634ccd198e..18cb5aa08f 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_VIA_K8T890),y) + ramstage-y += ctrl.c ramstage-y += dram.c ramstage-y += bridge.c @@ -10,3 +12,5 @@ ramstage-y += chrome.c chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc bootblock-y += romstrap.ld + +endif diff --git a/src/southbridge/via/vt8237r/Makefile.inc b/src/southbridge/via/vt8237r/Makefile.inc index de69ffda61..2630602ab4 100644 --- a/src/southbridge/via/vt8237r/Makefile.inc +++ b/src/southbridge/via/vt8237r/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_VIA_VT8237R),y) + ramstage-y += vt8237r.c ramstage-y += ctrl.c ramstage-y += ide.c @@ -27,3 +29,5 @@ ramstage-$(CONFIG_PIRQ_ROUTE) += pirq.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +endif |