diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-07 17:30:06 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-25 10:17:46 +0000 |
| commit | 0ee86f01f29ae17566857ff3fca54401c71be4db (patch) | |
| tree | 85e67aab65177c2ea9e9d6791bd53967755987eb /src | |
| parent | e80d17f602e841e826e0892e4e44c9e1a9810cc0 (diff) | |
soc/intel/baytrail/bootblock/bootblock.c: Move functions
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I34079985e165ce8d10c7a2b4f0dde15060132208
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43188
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/baytrail/bootblock/bootblock.c | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 62f42cd4d6..46f12e7646 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -9,25 +9,6 @@ #include <soc/spi.h> #include <soc/pm.h> -static void setup_mmconfig(void) -{ - uint32_t reg; - - /* - * Set up the MMCONF range. The register lives in the BUNIT. The IO variant of the - * config access needs to be used initially to properly configure as the IOSF access - * registers live in PCI config space. - */ - reg = 0; - /* Clear the extended register. */ - pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 1; - pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); - reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | - IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; - pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); -} - static void program_base_addresses(void) { uint32_t reg; @@ -56,6 +37,15 @@ static void program_base_addresses(void) pci_write_config32(lpc_dev, GBASE, reg); } +static void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} + static void spi_init(void) { void *scs = (void *)(SPI_BASE_ADDRESS + SCS); @@ -73,15 +63,6 @@ static void spi_init(void) write32(bcr, reg); } -static void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} - static void byt_config_com1_and_enable(void) { uint32_t reg; @@ -95,6 +76,25 @@ static void byt_config_com1_and_enable(void) score_select_func(UART_TXD_PAD, 1); } +static void setup_mmconfig(void) +{ + uint32_t reg; + + /* + * Set up the MMCONF range. The register lives in the BUNIT. The IO variant of the + * config access needs to be used initially to properly configure as the IOSF access + * registers live in PCI config space. + */ + reg = 0; + /* Clear the extended register. */ + pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | 1; + pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); + reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | + IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; + pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); +} + /* The distinction between nb/sb/cpu is not applicable here so just pick the one that is called first. */ void bootblock_early_northbridge_init(void) |