diff options
| author | EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> | 2022-10-03 16:24:04 +0800 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-11-09 22:35:27 +0000 |
| commit | 065c5870e4678367f5be7014361772c9d03933c8 (patch) | |
| tree | 42550d0b1a14f67fea6ce38536c0a8bcdada9452 /src | |
| parent | 7b73e85283bea7f456ab2f86ed1d1099eb88bc2f (diff) | |
ec/google/chromec: Expand EC share memory for DTTS
DTTS is Dynamic Thermal Table Switching Proposal.
DTTS needs one bit to save the body detection result from EC.
Define mode change STTB bit for Desktop (1) and laptop (0).
This bit is Switch thermal table by body detection status.
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/ec/google/chromeec/acpi/ec.asl | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 0914fdda37..32009028d3 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -56,6 +56,7 @@ Device (EC0) CHGL, 8, // Charger Current Limit TBMD, 1, // Tablet mode DDPN, 3, // Device DPTF Profile Number + STTB, 1, // Switch thermal table by body detection status // DFUD must be 0 for the other 31 values to be valid Offset (0x0a), DFUD, 1, // Device Features Undefined |