summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorReka Norman <rekanorman@chromium.org>2023-09-15 14:50:14 +1000
committerFelix Held <felix-coreboot@felixheld.de>2023-09-18 13:09:16 +0000
commit03e5cc54df0764c59a20404e08097f351b293ac0 (patch)
treed457faf3e5d1873d5e1f6afe9f2f2f41f72abceb /src
parent27780ab9a6ef7db5e62f02df6e4702bc5c1e8350 (diff)
mb/google/dedede/var/boxy: Update USB PLDs
Update PLDs to match the port layout: Front (left to right): C0, A1, A0 Left side: C1 Also enable the usb 3.1 device. BUG=b:264960828 TEST=USB2 and USB3 ports are peered correctly in the kernel: Before: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port4 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6 After: $ cd /sys/devices/pci0000:00/0000:00:14.0 $ ls -l $(find . -name peer) ./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1 ./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3 ./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4 ./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port2 ./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5 ./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6 ./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1 ./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port4 ./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2 ./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3 ./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5 ./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6 (Ports 5 and 6 are not used on boxy but are peered by default) Change-Id: I1563d9eaa27353c8c97225a0a6ecc238e9275ce2 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/dedede/variants/boxy/overridetree.cb13
1 files changed, 6 insertions, 7 deletions
diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb
index 2514efde68..c45d8f65aa 100644
--- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb
@@ -135,7 +135,6 @@ chip soc/intel/jasperlake
end # SA Thermal device
device pci 14.0 on
chip drivers/usb/acpi
- # TODO (b/264960828) verify PLD values
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C0""
@@ -146,19 +145,19 @@ chip soc/intel/jasperlake
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0""
register "type" = "UPC_TYPE_A"
- register "group" = "ACPI_PLD_GROUP(1, 2)"
+ register "group" = "ACPI_PLD_GROUP(1, 3)"
device usb 2.1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A1""
register "type" = "UPC_TYPE_A"
- register "group" = "ACPI_PLD_GROUP(1, 3)"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
device usb 2.2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- register "group" = "ACPI_PLD_GROUP(1, 4)"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
device usb 2.3 on end
end
chip drivers/usb/acpi
@@ -170,8 +169,8 @@ chip soc/intel/jasperlake
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- register "group" = "ACPI_PLD_GROUP(1, 2)"
- device usb 3.1 off end
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
+ device usb 3.1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A0""
@@ -182,7 +181,7 @@ chip soc/intel/jasperlake
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A1""
register "type" = "UPC_TYPE_USB3_A"
- register "group" = "ACPI_PLD_GROUP(1, 4)"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
device usb 3.3 on end
end
end