skylake: fill out gen_pmcon_* bitfields

Open coding bitfields is really annoying as no one knows
what they are unless you have a doc in front of you.
Fill in the bitfields for the GEN_PMCON_A and GEN_PMCON_B
registers.

BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.

Original-Change-Id: Id48de68eaa3896c17d5da2ffb0bcf17062f73e5e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290336
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I968be9736419e26a771e0a0c3c964d540fbb1efe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11182
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

2 files changed, 38 insertions, 4 deletions

diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h
index 5b5d663dac..5774d46a4b 100644
--- a/src/soc/intel/skylake/include/soc/pmc.h
+++ b/src/soc/intel/skylake/include/soc/pmc.h
@@ -32,12 +32,41 @@
 #define  SCIS_IRQ23		7
 #define PWRMBASE		0x48
 #define GEN_PMCON_A		0xa0
+#define  DC_PP_DIS		(1 << 30)
+#define  DSX_PP_DIS		(1 << 29)
+#define  AG3_PP_EN		(1 << 28)
+#define  SX_PP_EN		(1 << 27)
+#define  DISB			(1 << 23)
+#define  MEM_SR			(1 << 21)
+#define  MS4V			(1 << 18)
+#define  GBL_RST_STS		(1 << 16)
+#define  ALLOW_ICLK_PLL_SD_INC0	(1 << 15)
+#define  MPHY_CRICLK_GATE_OVER	(1 << 14)
+#define  ALLOW_OPI_PLL_SD_INC0	(1 << 13)
+#define  ALLOW_SPXB_CG_INC0	(1 << 12)
+#define  BIOS_PCI_EXP_EN	(1 << 10)
+#define  PWRBTN_LVL		(1 << 9)
+#define  ALLOW_L1LOW_C0		(1 << 7)
+#define  ALLOW_L1LOW_OPI_ON	(1 << 6)
 #define  SMI_LOCK		(1 << 4)
 #define GEN_PMCON_B		0xa4
 #define  SLP_STR_POL_LOCK	(1 << 18)
 #define  ACPI_BASE_LOCK		(1 << 17)
 #define  SUS_PWR_FLR		(1 << 14)
+#define  WOL_EN_OVRD		(1 << 13)
+#define  DIS_SLP_X_STRCH_SUS_UP		(1 << 12)
+#define  SLP_S3_MIN_ASST_WDTH_MASK	(0x3 << 10)
+#define  SLP_S3_MIN_ASST_WDTH_60USEC	(0 << 10)
+#define  SLP_S3_MIN_ASST_WDTH_1MS	(1 << 10)
+#define  SLP_S3_MIN_ASST_WDTH_50MS	(2 << 10)
+#define  SLP_S3_MIN_ASST_WDTH_2S	(3 << 10)
 #define  HOST_RST_STS		(1 << 9)
+#define  S4MAW_MASK		(0x3 << 4)
+#define  S4MAW_1S		(1 << 4)
+#define  S4MAW_2S		(2 << 4)
+#define  S4MAW_3S		(3 << 4)
+#define  S4MAW_4S		(0 << 4)
+#define  S4ASE			(1 << 3)
 #define  RTC_BATTERY_DEAD	(1 << 2)
 #define  PWR_FLR		(1 << 1)
 #define  SLEEP_AFTER_POWER_FAIL	(1 << 0)
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index b95441cc14..b62a28886b 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -39,12 +39,15 @@
 #endif
 
 static const struct reg_script pch_pmc_misc_init_script[] = {
-	/* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */
-	REG_PCI_RMW16(GEN_PMCON_B, ~((3 << 4)|(1 << 10)),
-			(1 << 3)|(1 << 11)|(1 << 12)),
+	/* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */
+	REG_PCI_RMW16(GEN_PMCON_B,
+			~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK),
+			S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS |
+			DIS_SLP_X_STRCH_SUS_UP),
+	/* Enable SCI and clear SLP requests. */
 	REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
 	/* Indicate DRAM init done for MRC */
-	REG_PCI_OR8(GEN_PMCON_A, (1 << 23)),
+	REG_PCI_OR8(GEN_PMCON_A, DISB),
 	REG_SCRIPT_END
 };
 
@@ -237,6 +240,8 @@ static void pmc_init(struct device *dev)
 	/* Initialize power management */
 	pch_power_options();
 
+	/* Note that certain bits may be cleared from running script as
+	 * certain bit fields are write 1 to clear. */
 	reg_script_run_on_dev(dev, pch_pmc_misc_init_script);
 	pch_set_acpi_mode();