diff options
| author | Hung-Te Lin <hungte@chromium.org> | 2013-07-08 18:41:02 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-12-12 22:06:08 +0100 |
| commit | c5aac958ae99bd556d077a49618e4a5daf0e65f3 (patch) | |
| tree | e072d39d7591269ae8de0026bd65b9f74c7509d4 /src | |
| parent | 356833d0b5379de6d960b479b6a9eb7d6b971b86 (diff) | |
exynos5250: Correct DDR3 Phy-reset value names.
The name "LPDDR3PHY_CTRL_PHY_RESET_OFF" is not appropriate because the real
phy-reset is a low-active pin, so "off(0)" will trigger "start to reset".
To prevent confusion, we should rename the constants to "RESET_ENABLE" and
"RESET_DISABLE".
Change-Id: Iccba5ef3a2e992f877dea90741f0308c161758c9
Reviewed-on: https://gerrit.chromium.org/gerrit/61081
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/4357
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 4 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5250/setup.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c index 554f4c2dc4..ae76b412f3 100644 --- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c @@ -33,8 +33,8 @@ static void reset_phy_ctrl(void) { struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - writel(LPDDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl); - writel(LPDDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); + writel(LPDDR3PHY_CTRL_PHY_RESET_ENABLE, &clk->lpddr3phy_ctrl); + writel(LPDDR3PHY_CTRL_PHY_RESET_DISABLE, &clk->lpddr3phy_ctrl); #if 0 /* diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h index 9f10786ada..2ed4f2200e 100644 --- a/src/cpu/samsung/exynos5250/setup.h +++ b/src/cpu/samsung/exynos5250/setup.h @@ -624,8 +624,8 @@ struct exynos5_phy_control; */ #define DECPROTXSET 0xFF -#define LPDDR3PHY_CTRL_PHY_RESET (1 << 0) -#define LPDDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) +#define LPDDR3PHY_CTRL_PHY_RESET_DISABLE (1 << 0) +#define LPDDR3PHY_CTRL_PHY_RESET_ENABLE (0 << 0 ) #define PHY_CON0_RESET_VAL 0x17020a40 #define P0_CMD_EN (1 << 14) |