diff options
| author | Cole Nelson <colex.nelson@intel.com> | 2018-06-12 10:02:49 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:26:27 +0000 |
| commit | 9d0950f154b07218e6c3bf6731279b587fe78a69 (patch) | |
| tree | d09df0b80c3e9e36a94ebbc93bf2fce03a1fce5b /src | |
| parent | 2b69b21c2db20ddce1f04e72b3eaa1d624540845 (diff) | |
soc/intel/{glk,apl}: ensure C1E is disabled after S3 resume
C1E is disabled by the kernel driver intel_idle at boot. This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.
Disable C1E for GLK as it is for APL. This gives a coherent state before
and after S3 resume.
TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).
Change-Id: I437cbaca75c539c2bc5cd801ab8df907e7447d10
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 4a7e40a33b..9337eb3417 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -53,11 +53,11 @@ static const struct reg_script core_msr_script[] = { /* Power Management I/O base address for I/O trapping to C-states */ REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), - /* Disable C1E */ - REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), /* Disable support for MONITOR and MWAIT instructions */ REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0), #endif + /* Disable C1E */ + REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0), /* * Enable and Lock the Advanced Encryption Standard (AES-NI) * feature register |