s2735 minor changes

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 17 insertions, 16 deletions

diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb
index c68fd37489..be05b56b27 100644
--- a/src/mainboard/tyan/s2735/Options.lb
+++ b/src/mainboard/tyan/s2735/Options.lb
@@ -10,7 +10,6 @@ uses IRQ_SLOT_COUNT
 uses HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_LOGICAL_CPUS
-#uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
 uses FALLBACK_SIZE
@@ -45,7 +44,8 @@ uses DEFAULT_CONSOLE_LOGLEVEL
 uses MAXIMUM_CONSOLE_LOGLEVEL
 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 
 ###
 ### Build options
@@ -53,8 +53,11 @@ uses CONFIG_CONSOLE_SERIAL8250
 
 ##
 ## ROM_SIZE is the size of boot ROM that this board will use.
-##
-default ROM_SIZE=524288
+#512K bytes
+#default ROM_SIZE=524288
+
+#1M bytes
+default ROM_SIZE=1048576
 
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
@@ -78,7 +81,6 @@ default HAVE_HARD_RESET=1
 #default HARD_RESET_DEVICE=4
 #default HARD_RESET_FUNCTION=0
 
-##
 ## Delay timer options
 ##
 default CONFIG_UDELAY_TSC=1
@@ -115,7 +117,6 @@ default LB_CKS_LOC=123
 default CONFIG_SMP=1
 default CONFIG_MAX_CPUS=4
 default CONFIG_LOGICAL_CPUS=1
-#default CONFIG_MAX_PHYSICAL_CPUS=2
 
 ##
 ## Build code to setup a generic IOAPIC
diff --git a/src/mainboard/tyan/s2735/auto.c b/src/mainboard/tyan/s2735/auto.c
index 091e74f321..5874d5ea35 100644
--- a/src/mainboard/tyan/s2735/auto.c
+++ b/src/mainboard/tyan/s2735/auto.c
@@ -70,7 +70,7 @@ static void main(unsigned long bist)
                 /* Skip this if there was a built in self test failure */
                 early_mtrr_init();
                 enable_lapic();
-                init_timer();
+//                init_timer();
 
         }
 
@@ -79,7 +79,7 @@ static void main(unsigned long bist)
         console_init();
 
         /* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
+//	report_bist_failure(bist);
 
 //        setup_default_resource_map();
 #if 0
@@ -87,9 +87,9 @@ static void main(unsigned long bist)
 #endif
 	if(!bios_reset_detected()) {
         	enable_smbus();
-#if 0
-//      	dump_spd_registers(&memctrl[0]);
-        	dump_smbus_registers();
+#if 1
+    		dump_spd_registers(&memctrl[0]);
+//        	dump_smbus_registers();
 #endif
 
 		memreset_setup();
@@ -114,7 +114,7 @@ static void main(unsigned long bist)
 #if 0
 	dump_pci_devices();
 #endif
-#if 0
+#if 1
 	dump_pci_device(PCI_DEV(0, 0, 0));
 #endif
 
@@ -130,7 +130,7 @@ static void main(unsigned long bist)
 #if  0
 	ram_check(0x00000000, msr.lo+(msr.hi<<32));
 #else
-#if 0
+#if 1
 	// Check 16MB of memory @ 0
 	ram_check(0x00000000, 0x01000000);
 #else
diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index 5922a1f34e..098ad5312a 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -127,7 +127,7 @@ static void pci_domain_set_resources(device_t dev)
 		
 		remaplimit_r = pci_read_config16(mc_dev, 0xc8);
 		remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
-		pci_write_config16(mc_dev, 0xc8, rempaplimit_r);
+		pci_write_config16(mc_dev, 0xc8, remaplimit_r);
 		
 		/* Report the memory regions */
 		idx = 10;
@@ -137,8 +137,8 @@ static void pci_domain_set_resources(device_t dev)
 			ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
 		}
 		if (remaplimitk >= remapbasek) {
-			ram_resource(dev, idx++, ramapbasek,
-				(reamplimitk + 64*1024) = remapbasek);
+			ram_resource(dev, idx++, remapbasek,
+				(remaplimitk + 64*1024) - remapbasek);
 		}
 	}
 	assign_resources(&dev->link[0]);