soc/intel/cannonlake: Force LPC IO decode settings

Force PCH LPC generic IO ranges are identical between PCH LPC pci config
space and DMI PCR registers. Reference documentation from 570374 chapter
2.4.1.

Bug=77944335
TEST=Boot up in OS in meowth board, using iotools to read LPC pci
config space offset 0x84~0x90 and compare with values read from DMI PCR
private register offset 0x2730~0x273c are identical.

Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25668
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 14 insertions, 0 deletions

diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index c02d66e54d..69a921feaf 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -30,6 +30,7 @@
 #include <intelblocks/pcr.h>
 #include <reg_script.h>
 #include <soc/iomap.h>
+#include <soc/lpc.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
 
@@ -68,6 +69,18 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
 }
 
 #if ENV_RAMSTAGE
+static void soc_mirror_dmi_pcr_io_dec(void)
+{
+	uint32_t io_dec_arr[] = {
+		pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC),
+		pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC),
+		pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC),
+		pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC),
+	};
+	/* Mirror these same settings in DMI PCR */
+	soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
+}
+
 static void pch_enable_ioapic(const struct device *dev)
 {
 	u32 reg32;
@@ -202,6 +215,7 @@ void lpc_soc_init(struct device *dev)
 	setup_i8259();
 	i8259_configure_irq_trigger(9, 1);
 	clock_gate_8254(dev);
+	soc_mirror_dmi_pcr_io_dec();
 }
 
 /* Fill up LPC IO resource structure inside SoC directory */