summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-07-25 02:46:39 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-07-26 21:17:50 +0000
commit89739baf531e26dc81420df4f943bf8c163a0c0d (patch)
tree61b363d8d6681e93af4d65bf7f0fd0276fa4bc8c /src
parent4d2db06ab5f52bd283673c08b40b3b87600d0674 (diff)
{sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits
We have definitions for the bits in the PCI COMMAND register. Use them. Also add spaces around bitwise operators, to comply with the code style. Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/baytrail/gfx.c2
-rw-r--r--src/soc/intel/baytrail/lpss.c3
-rw-r--r--src/soc/intel/baytrail/romstage/raminit.c2
-rw-r--r--src/soc/intel/baytrail/scc.c2
-rw-r--r--src/soc/intel/braswell/gfx.c2
-rw-r--r--src/soc/intel/braswell/lpss.c3
-rw-r--r--src/soc/intel/broadwell/sata.c3
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c4
-rw-r--r--src/southbridge/intel/bd82x6x/sata.c3
-rw-r--r--src/southbridge/intel/i82801dx/lpc.c4
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c4
-rw-r--r--src/southbridge/intel/i82801gx/sata.c3
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c4
-rw-r--r--src/southbridge/intel/i82801jx/lpc.c4
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c4
-rw-r--r--src/southbridge/intel/ibexpeak/sata.c3
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c4
-rw-r--r--src/southbridge/intel/lynxpoint/sata.c3
18 files changed, 39 insertions, 18 deletions
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 0da1fe49d3..0ee3cef591 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -205,7 +205,7 @@ static const struct reg_script gfx_init_script[] = {
static const struct reg_script gpu_pre_vbios_script[] = {
/* Make sure GFX is bus master with MMIO access */
- REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
+ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY),
/* Display */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0,
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index 08c3c05d85..afeb687be8 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -19,7 +19,8 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
- REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)),
+ REG_PCI_OR16(PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg,
LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN),
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 0b7a8c646d..7e6bcaba0f 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -36,7 +36,7 @@ int smbus_enable_iobar(uintptr_t base)
pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg);
/* Enable decode of I/O space. */
reg = pci_read_config16(smbus_dev, PCI_COMMAND);
- reg |= 0x1;
+ reg |= PCI_COMMAND_IO;
pci_write_config16(smbus_dev, PCI_COMMAND, reg);
/* Enable Host Controller */
reg = pci_read_config8(smbus_dev, 0x40);
diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c
index f178e83d28..3b19f1b277 100644
--- a/src/soc/intel/baytrail/scc.c
+++ b/src/soc/intel/baytrail/scc.c
@@ -74,7 +74,7 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
REG_PCI_OR16(PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg,
SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN),
diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c
index 1bd0033313..7599329b61 100644
--- a/src/soc/intel/braswell/gfx.c
+++ b/src/soc/intel/braswell/gfx.c
@@ -14,7 +14,7 @@
static const struct reg_script gpu_pre_vbios_script[] = {
/* Make sure GFX is bus master with MMIO access */
- REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
+ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY),
REG_SCRIPT_END
};
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c
index 7ff42c35df..961d405156 100644
--- a/src/soc/intel/braswell/lpss.c
+++ b/src/soc/intel/braswell/lpss.c
@@ -19,7 +19,8 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
- REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)),
+ REG_PCI_OR16(PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg,
LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN),
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c
index 5ddccc52f0..e7135f79b0 100644
--- a/src/soc/intel/broadwell/sata.c
+++ b/src/soc/intel/broadwell/sata.c
@@ -36,7 +36,8 @@ static void sata_init(struct device *dev)
printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n");
/* Enable BARs */
- pci_write_config16(dev, PCI_COMMAND, 0x0007);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* Set Interrupt Line */
/* Interrupt Pin is set by D31IP.PIP */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 2efddd89a1..2407d92dc1 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -520,7 +520,9 @@ static void lpc_init(struct device *dev)
report_pch_info(dev);
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
pch_enable_ioapic(dev);
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 63801a213e..484f0f11a2 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -108,7 +108,8 @@ static void sata_init(struct device *dev)
/* SATA configuration */
/* Enable BARs */
- pci_write_config16(dev, PCI_COMMAND, 0x0007);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* AHCI */
if (sata_mode == 0) {
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 3a71dbcf6b..dec12666fc 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -253,7 +253,9 @@ static void enable_hpet(struct device *dev)
static void lpc_init(struct device *dev)
{
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
i82801dx_enable_acpi(dev);
/* IO APIC initialization. */
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 9b32f6cfd9..0c7678117f 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -347,7 +347,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "i82801gx: %s\n", __func__);
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
i82801gx_enable_ioapic(dev);
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 6efdef76cb..715d670ae2 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -88,7 +88,8 @@ static void sata_init(struct device *dev)
ports = get_ich7_sata_ports();
/* Enable BARs */
- pci_write_config16(dev, PCI_COMMAND, 0x0007);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
switch (config->sata_mode) {
case SATA_MODE_IDE_LEGACY_COMBINED:
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index a2df123bc9..6fe9bb9470 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -357,7 +357,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "i82801ix: %s\n", __func__);
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
i82801ix_enable_apic(dev);
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index fceeb3f80e..a8b53706c1 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -361,7 +361,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "i82801jx: %s\n", __func__);
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
i82801jx_enable_apic(dev);
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 7e99613a28..230d5eb29f 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -439,7 +439,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
pch_enable_ioapic(dev);
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 357ad5fc99..21371495eb 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -49,7 +49,8 @@ static void sata_init(struct device *dev)
/* SATA configuration */
/* Enable BARs */
- pci_write_config16(dev, PCI_COMMAND, 0x0007);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (sata_mode == 0) {
/* AHCI */
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index f3298b00c9..7082a79d31 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -505,7 +505,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
pch_enable_ioapic(dev);
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 47e6f9be68..2f903f04fb 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -41,7 +41,8 @@ static void sata_init(struct device *dev)
/* SATA configuration */
/* Enable BARs */
- pci_write_config16(dev, PCI_COMMAND, 0x0007);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (config->ide_legacy_combined) {
printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 18:50:24 +0000