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authorLee Leahy <leroy.p.leahy@intel.com>2015-09-17 11:53:27 -0700
committerAaron Durbin <adurbin@gmail.com>2015-10-11 23:58:34 +0000
commit8475f2d0c554a67741824a4a9d84ddc0c31a0778 (patch)
treeafc4f51f9d9688168de5697a371a784db790b7f8 /src
parentf45eb062da5a78425d52732b0a0a988b30457c24 (diff)
skylake: Leave SPI controller enabled
Leave the SPI controller enabled upon boot block exit. BRANCH=none BUG=chrome-os-partner:44827 TEST=Build and run on kunimitsu Change-Id: I5b10d7cc8d5d350282206abe6a945bab66f97ada Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: http://review.coreboot.org/11825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/bootblock/cpu.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index b29acb75ef..3a29972370 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -120,11 +120,6 @@ static void set_pch_cpu_strap(u8 flex_ratio)
ssl = read32(spibar + SPIBAR_RESET_LOCK);
ssl |= SPIBAR_RESET_LOCK_ENABLE;
write32(spibar + SPIBAR_RESET_LOCK, ssl);
-
- /* Disable SPI Controller MMIO space */
- pcireg = pci_read_config8(dev, PCI_COMMAND);
- pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
- pci_write_config8(dev, PCI_COMMAND, pcireg);
}
static void set_flex_ratio_to_tdp_nominal(void)