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authorhuang lin <hl@rock-chips.com>2014-08-26 17:31:28 +0800
committerPatrick Georgi <pgeorgi@google.com>2015-03-24 15:24:52 +0100
commit817e455d38d9ec6730fa27ee13e9ae123b1dc632 (patch)
tree54942662adf8783d51a6165352f8715e810fbf14 /src
parent7333e1fbc392e07f1715a70232eae11aa619b00c (diff)
add make_idb.py & update bootblock
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: Ica7b2bf2cf649c2731933ce59a263692bb2c0282 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ba9c36daedc749748f45e68a84f8c34c636adb1c Original-Change-Id: Ia0e4e39d4391674f25e630b40913eb99ff3f75c4 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8862 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/veyron/Kconfig4
-rw-r--r--src/soc/rockchip/rk3288/Kconfig4
-rw-r--r--src/soc/rockchip/rk3288/Makefile.inc10
-rw-r--r--src/soc/rockchip/rk3288/bootblock.c8
4 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig
index bbbc617d92..0ae425e2a3 100644
--- a/src/mainboard/google/veyron/Kconfig
+++ b/src/mainboard/google/veyron/Kconfig
@@ -44,6 +44,10 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
default 1
+config BOOT_MEDIA_SPI_BUS
+ int
+ default 2
+
config DRAM_DMA_START
hex
default 0x10000000
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
index 0fadefd283..359ce2f57d 100644
--- a/src/soc/rockchip/rk3288/Kconfig
+++ b/src/soc/rockchip/rk3288/Kconfig
@@ -54,6 +54,10 @@ config BOOTBLOCK_CPU_INIT
# 0xFF71_3000 CBFS mapping cache (20K)
# 0xFF71_7FFF End of iRAM.
+config SYS_SRAM_BASE
+ hex "SRAM base address"
+ default 0xFF700000
+
config SYS_SDRAM_BASE
hex "SDRAM base address"
default 0x00000000
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index e0f32242a5..7d5b3a5767 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -17,6 +17,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+IDBTOOL = util/rockchip/make_idb.py
+
#bootblock-y += bootblock.c
bootblock-y += cbmem.c
bootblock-y += timer.c
@@ -43,3 +45,11 @@ ramstage-y += clock.c
ramstage-y += spi.c
ramstage-y += media.c
ramstage-$(CONFIG_DRIVERS_UART) += uart.c
+
+$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
+ cp $< $@
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+ @printf "Generating: $(subst $(obj)/,,$(@))\n"
+ @mkdir -p $(dir $@)
+ @$(IDBTOOL) --from=$< --to=$@ --enable-align
diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c
index 04afae5529..76a91d234d 100644
--- a/src/soc/rockchip/rk3288/bootblock.c
+++ b/src/soc/rockchip/rk3288/bootblock.c
@@ -19,12 +19,20 @@
#include <console/console.h>
#include <arch/cache.h>
+#include <arch/io.h>
#include <bootblock_common.h>
#include "timer.h"
#include "clock.h"
+#include "grf.h"
+#include "spi.h"
static void bootblock_cpu_init(void)
{
+ writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
+ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
+ writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
rk3288_init_timer();
+ console_init();
rkclk_init();
+ rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS);
}