amd/torpedo: Switch away from AGESA_LEGACY_WRAPPER

Change-Id: Iac0998a56b4e297c512fcba98d3dbb4253c9b526
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

4 files changed, 9 insertions, 12 deletions

diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig
index 348f995ec6..5c85c4b74e 100644
--- a/src/mainboard/amd/torpedo/Kconfig
+++ b/src/mainboard/amd/torpedo/Kconfig
@@ -17,7 +17,6 @@ if BOARD_AMD_TORPEDO
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select AGESA_LEGACY_WRAPPER
 	select CPU_AMD_AGESA_FAMILY12
 	select NORTHBRIDGE_AMD_AGESA_FAMILY12
 	select SOUTHBRIDGE_AMD_CIMX_SB900
diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c
index 3c20047a31..8dc5affb63 100644
--- a/src/mainboard/amd/torpedo/OemCustomize.c
+++ b/src/mainboard/amd/torpedo/OemCustomize.c
@@ -16,9 +16,10 @@
 #include "PlatformGnbPcieComplex.h"
 
 #include <string.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
+#include "amdlib.h"
 
 #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE
 
@@ -105,7 +106,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Llano = {
  **/
 /*---------------------------------------------------------------------------------------*/
 
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
 	AGESA_STATUS         Status;
 	VOID                 *LlanoPcieComplexListPtr;
@@ -159,7 +160,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
 
 	InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr;
 	InitEarly->GnbConfig.PsppPolicy      = 0;
-	return AGESA_SUCCESS;
 }
 
 /*----------------------------------------------------------------------------------------
@@ -173,12 +173,13 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
  *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
  *  use its default conservative settings.
  */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
 	NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
 	NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
 	PSO_END
 };
 
-const struct OEM_HOOK OemCustomize = {
-	.InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
index 001ed169e7..ee8e4996f9 100644
--- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
@@ -16,10 +16,6 @@
 #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
 #define _PLATFORM_GNB_PCIE_COMPLEX_H
 
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-
 //GNB GPP Port4
 #define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 3454ef8744..e4fcdfed58 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <device/pnp_def.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <superio/smsc/kbc1100/kbc1100.h>