sb/intel/lynxpoint/sata: Always use AHCI mode

The other two modes are not used by any mainboard, and the code seems to
be copied from older southbridges. As the code looks incorrect, drop it.

Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>

9 files changed, 84 insertions, 182 deletions

diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb
index d257f18bc6..024d1f0e1f 100644
--- a/src/mainboard/asrock/b85m_pro4/devicetree.cb
+++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb
@@ -27,7 +27,6 @@ chip northbridge/intel/haswell
 
 		chip southbridge/intel/lynxpoint
 			register "gen1_dec"      = "0x000c0291"	# Super I/O HWM
-			register "sata_ahci"     = "1"
 			register "sata_port_map" = "0x3f"
 
 			device pci 14.0 on  end		# xHCI controller
diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb
index 8f368961de..45119f9476 100644
--- a/src/mainboard/asrock/h81m-hds/devicetree.cb
+++ b/src/mainboard/asrock/h81m-hds/devicetree.cb
@@ -35,7 +35,6 @@ chip northbridge/intel/haswell
 		end
 
 		chip southbridge/intel/lynxpoint
-			register "sata_ahci" = "1"
 			register "sata_port_map" = "0x33"
 
 			register "gen1_dec" = "0x00000295" # Super I/O HWM
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb
index 8fdfbd79a0..176fced5ed 100644
--- a/src/mainboard/google/beltino/devicetree.cb
+++ b/src/mainboard/google/beltino/devicetree.cb
@@ -45,8 +45,6 @@ chip northbridge/intel/haswell
 			register "gpe0_en_3" = "0x00000000"
 			register "gpe0_en_4" = "0x00000000"
 
-			register "ide_legacy_combined" = "0x0"
-			register "sata_ahci" = "0x1"
 			register "sata_port_map" = "0x1"
 			register "sata_devslp_disable" = "0x1"
 
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index 200721b8ef..a6fab83a5b 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -52,8 +52,6 @@ chip northbridge/intel/haswell
 			register "gpe0_en_3" = "0x00000000"
 			register "gpe0_en_4" = "0x00000000"
 
-			register "ide_legacy_combined" = "0x0"
-			register "sata_ahci" = "0x1"
 			register "sata_port_map" = "0x1"
 
 			register "sio_acpi_mode" = "1"
diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb
index 6345090c7a..784c926d5f 100644
--- a/src/mainboard/intel/baskingridge/devicetree.cb
+++ b/src/mainboard/intel/baskingridge/devicetree.cb
@@ -41,8 +41,6 @@ chip northbridge/intel/haswell
 			register "alt_gp_smi_en" = "0x0000"
 			register "gpe0_en_1" = "0x4000"
 
-			register "ide_legacy_combined" = "0x0"
-			register "sata_ahci" = "0x1"
 			register "sata_port_map" = "0x3f"
 
 			# SuperIO range is 0x700-0x73f
diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb
index 8c356816ab..9359bb4e5d 100644
--- a/src/mainboard/lenovo/t440p/devicetree.cb
+++ b/src/mainboard/lenovo/t440p/devicetree.cb
@@ -37,7 +37,6 @@ chip northbridge/intel/haswell
 			register "gen4_dec" = "0x000c06a1"
 			register "gpi13_routing" = "2"
 			register "gpi1_routing" = "2"
-			register "sata_ahci" = "1"
 			# 0(HDD), 1(M.2), 5(ODD)
 			register "sata_port_map" = "0x23"
 			device pci 14.0 on end # xHCI Controller
diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb
index ffcc56d15c..6d64a90221 100644
--- a/src/mainboard/supermicro/x10slm-f/devicetree.cb
+++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb
@@ -26,7 +26,6 @@ chip northbridge/intel/haswell
 		device pci 03.0 off end # Mini-HD audio
 
 		chip southbridge/intel/lynxpoint
-			register "sata_ahci" = "1"
 			register "sata_port_map" = "0x3f"
 
 			register "gen1_dec" = "0x00000295" # Super I/O HWM
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index 40d0460419..89bbb1ce0c 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -38,9 +38,7 @@ struct southbridge_intel_lynxpoint_config {
 	uint32_t gpe0_en_4;
 	uint32_t alt_gp_smi_en;
 
-	/* IDE configuration */
-	uint32_t ide_legacy_combined;
-	uint32_t sata_ahci;
+	/* SATA configuration */
 	uint8_t sata_port_map;
 	uint32_t sata_port0_gen3_tx;
 	uint32_t sata_port1_gen3_tx;
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index e1a2fa5a57..c9c7f2cadb 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -29,6 +29,9 @@ static void sata_init(struct device *dev)
 {
 	u32 reg32;
 	u16 reg16;
+
+	u32 *abar;
+
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 
@@ -44,170 +47,87 @@ static void sata_init(struct device *dev)
 	/* Enable memory space decoding for ABAR */
 	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 
-	if (config->ide_legacy_combined) {
-		printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
-
-		/* No AHCI: clear AHCI base */
-		pci_write_config32(dev, 0x24, 0);
-
-		/* And without AHCI BAR no memory decoding */
-		pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY);
-
-		pci_write_config8(dev, 0x09, 0x80);
-
-		/* Set timings */
-		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
-				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
-		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
-				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
-				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
-
-		/* Sync DMA */
-		pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
-		pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
-
-		/* Set IDE I/O Configuration */
-		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
-		pci_write_config32(dev, IDE_CONFIG, reg32);
-
-		/* Port enable */
-		reg16 = pci_read_config16(dev, 0x92);
-		reg16 &= ~0x3f;
-		reg16 |= config->sata_port_map;
-		pci_write_config16(dev, 0x92, reg16);
-
-		/* SATA Initialization register */
-		pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
-	} else if (config->sata_ahci) {
-		u32 *abar;
-
-		printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
-
-		/* Set Interrupt Line */
-		/* Interrupt Pin is set by D31IP.PIP */
-		pci_write_config8(dev, INTR_LN, 0x0a);
-
-		/* Set timings */
-		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
-				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
-				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
-		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
-				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
-
-		/* Sync DMA */
-		pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
-		pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
-
-		/* Set IDE I/O Configuration */
-		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
-		pci_write_config32(dev, IDE_CONFIG, reg32);
-
-		/* for AHCI, Port Enable is managed in memory mapped space */
-		reg16 = pci_read_config16(dev, 0x92);
-		reg16 &= ~0x3f;
-		reg16 |= 0x8000 | config->sata_port_map;
-		pci_write_config16(dev, 0x92, reg16);
-		udelay(2);
-
-		/* Setup register 98h */
-		reg32 = pci_read_config16(dev, 0x98);
-		reg32 |= 1 << 19;    /* BWG step 6 */
-		reg32 |= 1 << 22;    /* BWG step 5 */
-		reg32 &= ~(0x3f << 7);
-		reg32 |= 0x04 << 7;  /* BWG step 7 */
-		reg32 |= 1 << 20;    /* BWG step 8 */
-		reg32 &= ~(0x03 << 5);
-		reg32 |= 1 << 5;     /* BWG step 9 */
-		reg32 |= 1 << 18;    /* BWG step 10 */
-		reg32 |= 1 << 29;    /* BWG step 11 */
-		if (pch_is_lp()) {
-			reg32 &= ~((1 << 31) | (1 << 30));
-			reg32 |= 1 << 23;
-			reg32 |= 1 << 24; /* Disable listen mode (hotplug) */
-		}
-		pci_write_config32(dev, 0x98, reg32);
-
-		/* Setup register 9Ch: Disable alternate ID and BWG step 12 */
-		pci_write_config16(dev, 0x9c, 1 << 5);
-
-		/* SATA Initialization register */
-		reg32 = 0x183;
-		reg32 |= (config->sata_port_map ^ 0x3f) << 24;
-		reg32 |= (config->sata_devslp_mux & 1) << 15;
-		pci_write_config32(dev, 0x94, reg32);
-
-		/* Initialize AHCI memory-mapped space */
-		abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
-		printk(BIOS_DEBUG, "ABAR: %p\n", abar);
-		/* CAP (HBA Capabilities) : enable power management */
-		reg32 = read32(abar + 0x00);
-		reg32 |= 0x0c006000;  // set PSC+SSC+SALP+SSS
-		reg32 &= ~0x00020060; // clear SXS+EMS+PMS
-		if (pch_is_lp())
-			reg32 |= (1 << 18);   // SAM: SATA AHCI MODE ONLY
-		write32(abar + 0x00, reg32);
-		/* PI (Ports implemented) */
-		write32(abar + 0x03, config->sata_port_map);
-		(void)read32(abar + 0x03); /* Read back 1 */
-		(void)read32(abar + 0x03); /* Read back 2 */
-		/* CAP2 (HBA Capabilities Extended)*/
-		reg32 = read32(abar + 0x09);
-		/* Enable DEVSLP */
-		if (pch_is_lp()) {
-			if (config->sata_devslp_disable)
-				reg32 &= ~(1 << 3);
-			else
-				reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
-		} else {
-			reg32 &= ~0x00000002;
-		}
-		write32(abar + 0x09, reg32);
+	printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
+
+	/* Set Interrupt Line */
+	/* Interrupt Pin is set by D31IP.PIP */
+	pci_write_config8(dev, INTR_LN, 0x0a);
+
+	/* Set timings */
+	pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+			IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+			IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+	pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+			IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+
+	/* Sync DMA */
+	pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
+	pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
+
+	/* Set IDE I/O Configuration */
+	reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+	pci_write_config32(dev, IDE_CONFIG, reg32);
+
+	/* for AHCI, Port Enable is managed in memory mapped space */
+	reg16 = pci_read_config16(dev, 0x92);
+	reg16 &= ~0x3f;
+	reg16 |= 0x8000 | config->sata_port_map;
+	pci_write_config16(dev, 0x92, reg16);
+	udelay(2);
+
+	/* Setup register 98h */
+	reg32 = pci_read_config16(dev, 0x98);
+	reg32 |= 1 << 19;    /* BWG step 6 */
+	reg32 |= 1 << 22;    /* BWG step 5 */
+	reg32 &= ~(0x3f << 7);
+	reg32 |= 0x04 << 7;  /* BWG step 7 */
+	reg32 |= 1 << 20;    /* BWG step 8 */
+	reg32 &= ~(0x03 << 5);
+	reg32 |= 1 << 5;     /* BWG step 9 */
+	reg32 |= 1 << 18;    /* BWG step 10 */
+	reg32 |= 1 << 29;    /* BWG step 11 */
+	if (pch_is_lp()) {
+		reg32 &= ~((1 << 31) | (1 << 30));
+		reg32 |= 1 << 23;
+		reg32 |= 1 << 24; /* Disable listen mode (hotplug) */
+	}
+	pci_write_config32(dev, 0x98, reg32);
+
+	/* Setup register 9Ch: Disable alternate ID and BWG step 12 */
+	pci_write_config16(dev, 0x9c, 1 << 5);
+
+	/* SATA Initialization register */
+	reg32 = 0x183;
+	reg32 |= (config->sata_port_map ^ 0x3f) << 24;
+	reg32 |= (config->sata_devslp_mux & 1) << 15;
+	pci_write_config32(dev, 0x94, reg32);
+
+	/* Initialize AHCI memory-mapped space */
+	abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+	printk(BIOS_DEBUG, "ABAR: %p\n", abar);
+	/* CAP (HBA Capabilities) : enable power management */
+	reg32 = read32(abar + 0x00);
+	reg32 |= 0x0c006000;  // set PSC+SSC+SALP+SSS
+	reg32 &= ~0x00020060; // clear SXS+EMS+PMS
+	if (pch_is_lp())
+		reg32 |= (1 << 18);   // SAM: SATA AHCI MODE ONLY
+	write32(abar + 0x00, reg32);
+	/* PI (Ports implemented) */
+	write32(abar + 0x03, config->sata_port_map);
+	(void)read32(abar + 0x03); /* Read back 1 */
+	(void)read32(abar + 0x03); /* Read back 2 */
+	/* CAP2 (HBA Capabilities Extended)*/
+	reg32 = read32(abar + 0x09);
+	/* Enable DEVSLP */
+	if (pch_is_lp()) {
+		if (config->sata_devslp_disable)
+			reg32 &= ~(1 << 3);
+		else
+			reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
 	} else {
-		printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
-
-		/* No AHCI: clear AHCI base */
-		pci_write_config32(dev, 0x24, 0);
-
-		/* And without AHCI BAR no memory decoding */
-		pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY);
-
-		/*
-		 * Native mode capable on both primary and secondary (0xa)
-		 * or'ed with enabled (0x50) = 0xf
-		 *
-		 * FIXME: Does not match the code.
-		 */
-		pci_write_config8(dev, 0x09, 0x8f);
-
-		/* Set Interrupt Line */
-		/* Interrupt Pin is set by D31IP.PIP */
-		pci_write_config8(dev, INTR_LN, 0xff);
-
-		/* Set timings */
-		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
-				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
-				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
-		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
-				IDE_SITRE | IDE_ISP_3_CLOCKS |
-				IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
-
-		/* Sync DMA */
-		pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
-		pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
-
-		/* Set IDE I/O Configuration */
-		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
-		pci_write_config32(dev, IDE_CONFIG, reg32);
-
-		/* Port enable */
-		reg16 = pci_read_config16(dev, 0x92);
-		reg16 &= ~0x3f;
-		reg16 |= config->sata_port_map;
-		pci_write_config16(dev, 0x92, reg16);
-
-		/* SATA Initialization register */
-		pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
+		reg32 &= ~0x00000002;
 	}
+	write32(abar + 0x09, reg32);
 
 	/* Set Gen3 Transmitter settings if needed */
 	if (config->sata_port0_gen3_tx)
@@ -290,7 +210,6 @@ static void sata_enable(struct device *dev)
 {
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
-	u16 map = 0;
 
 	if (!config)
 		return;
@@ -299,12 +218,7 @@ static void sata_enable(struct device *dev)
 	 * Set SATA controller mode early so the resource allocator can
 	 * properly assign IO/Memory resources for the controller.
 	 */
-	if (config->sata_ahci)
-		map = 0x0060;
-
-	map |= (config->sata_port_map ^ 0x3f) << 8;
-
-	pci_write_config16(dev, 0x90, map);
+	pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ 0x3f) << 8);
 }
 
 static struct device_operations sata_ops = {