soc/intel/*/chip: Remove unused devicetree entry

InternalGfx isn't used so drop it.

Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

10 files changed, 1 insertions, 12 deletions

diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index aeacaa48dd..f3ce6286be 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -30,7 +30,6 @@ chip soc/intel/cannonlake
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
-	register "InternalGfx" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "PchPmSlpS3MinAssert" = "3"  # 50ms
 	register "PchPmSlpS4MinAssert" = "4"  # 4s
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index dddbca421d..01c0d234f9 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -18,7 +18,6 @@ chip soc/intel/cannonlake
 	register "gen3_dec" = "0x00fc0901"
 
 	# FSP configuration
-	register "InternalGfx" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SataSalpSupport" = "1"
 	register "SataMode" = "Sata_AHCI"
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 8562046237..74529d049d 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -19,7 +19,6 @@ chip soc/intel/cannonlake
 	register "SataMode" = "Sata_AHCI"
 	register "SataPortsEnable[2]" = "1"
 	register "SataPortsDevSlp[2]" = "1"
-	register "InternalGfx" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "PchPmSlpS3MinAssert" = "3"  # 50ms
 	register "PchPmSlpS4MinAssert" = "4"  # 4s
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 1334749542..519c3eb6d9 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -23,7 +23,6 @@ chip soc/intel/cannonlake
 	register "SataPortsDevSlp[0]" = "1"
 	register "SataPortsDevSlp[1]" = "1"
 	register "SataPortsDevSlp[2]" = "1"
-	register "InternalGfx" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "PchPmSlpS3MinAssert" = "3"  # 50ms
 	register "PchPmSlpS4MinAssert" = "4"  # 4s
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
index 1bf65ff5a1..025510e7ce 100644
--- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
@@ -161,9 +161,7 @@ chip soc/intel/cannonlake
 
 
 	device domain 0 on
-		device pci 02.0 on      # Integrated Graphics Device
-			register "InternalGfx" = "1"
-		end
+		device pci 02.0 on end	# Integrated Graphics Device
 		device pci 14.3 on
 			chip drivers/wifi/generic
 				register "wake" = "PME_B0_EN_BIT"
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 7f428a21f0..dc24e9bd8f 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -230,7 +230,6 @@ struct soc_intel_cannonlake_config {
 
 	/* Gfx related */
 	uint8_t IgdDvmt50PreAlloc;
-	uint8_t InternalGfx;
 	uint8_t SkipExtGfxScan;
 
 	uint32_t GraphicsConfigPtr;
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index 26d0f0d666..7cd29b4f40 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -140,7 +140,6 @@ struct soc_intel_elkhartlake_config {
 
 	/* Gfx related */
 	uint8_t IgdDvmt50PreAlloc;
-	uint8_t InternalGfx;
 	uint8_t SkipExtGfxScan;
 
 	uint32_t GraphicsConfigPtr;
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index e1b697e3c7..956793acd5 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -152,7 +152,6 @@ struct soc_intel_icelake_config {
 
 	/* Gfx related */
 	uint8_t IgdDvmt50PreAlloc;
-	uint8_t InternalGfx;
 	uint8_t SkipExtGfxScan;
 
 	uint32_t GraphicsConfigPtr;
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 5e9053063b..f157f9218b 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -141,7 +141,6 @@ struct soc_intel_jasperlake_config {
 
 	/* Gfx related */
 	uint8_t IgdDvmt50PreAlloc;
-	uint8_t InternalGfx;
 	uint8_t SkipExtGfxScan;
 
 	uint32_t GraphicsConfigPtr;
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index f752b5f415..6a48ad03be 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -261,7 +261,6 @@ struct soc_intel_tigerlake_config {
 
 	/* Gfx related */
 	uint8_t IgdDvmt50PreAlloc;
-	uint8_t InternalGfx;
 	uint8_t SkipExtGfxScan;
 
 	uint32_t GraphicsConfigPtr;