Use DIMM0 et al in lots more places instead of hardocding values.

The (0xa << 3) expression equals 0x50, i.e. DIMM0.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

66 files changed, 204 insertions, 186 deletions

diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index 8977b27bd4..c1909c1ecb 100644
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -65,7 +65,7 @@ void main(unsigned long bist)
 	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
-		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 
 	SystemPreInit();
diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index 1211610421..4704cc2fe0 100644
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -62,7 +62,7 @@ void main(unsigned long bist)
 	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
-		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 
 	SystemPreInit();
diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c
index e08d967471..c7c45ccc58 100644
--- a/src/mainboard/amd/rumba/romstage.c
+++ b/src/mainboard/amd/rumba/romstage.c
@@ -35,7 +35,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl [] = {
-		{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 
 	SystemPreInit();
diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c
index 7438b8438b..3cc9553d25 100644
--- a/src/mainboard/arima/hdama/romstage.c
+++ b/src/mainboard/arima/hdama/romstage.c
@@ -24,6 +24,7 @@
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
 
@@ -85,11 +86,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
-		(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-		(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-		(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-		(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+		DIMM4, DIMM6, 0, 0,
+		DIMM5, DIMM7, 0, 0,
 #endif
 	};
 
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index 8303b15f49..37cb71abd7 100644
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -78,7 +78,7 @@ void main(unsigned long bist)
 
 	msr_t msr;
 	static const struct mem_controller memctrl[] = {
-		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 
 	SystemPreInit();
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index b9253aa4c4..155f414668 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -48,6 +48,7 @@
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
@@ -93,11 +94,11 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
-		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
-		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-		(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
-		(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+		DIMM4, DIMM6, 0, 0,
+		DIMM5, DIMM7, 0, 0,
 #endif
 	};
 
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 1903adc97d..fbefe34c0e 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -46,6 +46,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
@@ -154,11 +155,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
 		// Node 0
-		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
-		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
 		// Node 1
-		(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
-		(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+		DIMM4, DIMM6, 0, 0,
+		DIMM5, DIMM7, 0, 0,
 	};
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 1903adc97d..fbefe34c0e 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -46,6 +46,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
@@ -154,11 +155,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
 		// Node 0
-		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
-		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
 		// Node 1
-		(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
-		(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+		DIMM4, DIMM6, 0, 0,
+		DIMM5, DIMM7, 0, 0,
 	};
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 91a75adfb8..e0b61fcbdb 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -49,6 +49,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
 #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
@@ -128,11 +129,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
 		// Node 0
-		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
-		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
 		// Node 1
-		(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
-		(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+		DIMM4, DIMM6, 0, 0,
+		DIMM5, DIMM7, 0, 0,
 	};
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 7237568b15..d54d2d5efb 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -49,6 +49,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
 #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
@@ -231,11 +232,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
 		// Node 0
-		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
-		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
 		// Node 1
-		(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
-		(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+		DIMM4, DIMM6, 0, 0,
+		DIMM5, DIMM7, 0, 0,
 	};
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c
index 0d8746bcfc..32654d8ab3 100644
--- a/src/mainboard/bcom/winnetp680/romstage.c
+++ b/src/mainboard/bcom/winnetp680/romstage.c
@@ -32,6 +32,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include <lib.h>
+#include <spd.h>
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c
index a935ffc13d..0b64c9d9eb 100644
--- a/src/mainboard/dell/s1850/romstage.c
+++ b/src/mainboard/dell/s1850/romstage.c
@@ -19,6 +19,7 @@
 #include "s1850_fixups.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
 
@@ -149,10 +150,7 @@ static void main(unsigned long bist)
 	u16 w;
 	u32 l;
 	int do_reset;
-	/*
-	 *
-	 *
-	 */
+
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
@@ -164,8 +162,8 @@ static void main(unsigned long bist)
 			*/
 			/* the wiring on this part is really messed up */
 			/* this is my best guess so far */
-			.channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
-			.channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
+			.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
+			.channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
 		}
 	};
 
diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c
index 40a0626401..5e782ed1b0 100644
--- a/src/mainboard/digitallogic/adl855pc/romstage.c
+++ b/src/mainboard/digitallogic/adl855pc/romstage.c
@@ -15,6 +15,7 @@
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -32,7 +33,7 @@ void main(unsigned long bist)
 	static const struct mem_controller memctrl[] = {
 		{
 			.d0 = PCI_DEV(0, 0, 1),
-			.channel0 = { (0xa<<3)|0, 0 },
+			.channel0 = { DIMM0, 0 },
 		},
 	};
 
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index 6cf6ec6f19..8b5f00d4fb 100644
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -45,7 +45,7 @@ void main(unsigned long bist)
 	post_code(0x01);
 
 	static const struct mem_controller memctrl [] = {
-		{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 
 	SystemPreInit();
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index a93179a42e..4a6971be4d 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -37,6 +37,7 @@
 
 #include <console/console.h>
 #include <usbdebug.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -134,11 +135,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
 			// Node 0
-			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+			DIMM0, DIMM2, 0, 0,
+			DIMM1, DIMM3, 0, 0,
 			// Node 1
-			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+			DIMM4, DIMM6, 0, 0,
+			DIMM5, DIMM7, 0, 0,
 	};
 
         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index d606040d2c..7665c7b622 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -35,6 +35,7 @@
 
 #include <console/console.h>
 #include <usbdebug.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -131,11 +132,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
 			// Node 0
-			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+			DIMM0, DIMM2, 0, 0,
+			DIMM1, DIMM3, 0, 0,
 			// Node 1
-			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+			DIMM4, DIMM6, 0, 0,
+			DIMM5, DIMM7, 0, 0,
 	};
 
         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index d2e393cbe1..70f829a07f 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -146,8 +146,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
 		// first node
-		 DIMM0, DIMM2, 0, 0,
-		 DIMM1, DIMM3, 0, 0,
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
 
 		// second node
 		DIMM4, DIMM6, 0, 0,
diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c
index 2ec5a82ddb..75fcee2e22 100644
--- a/src/mainboard/ibm/e325/romstage.c
+++ b/src/mainboard/ibm/e325/romstage.c
@@ -25,6 +25,7 @@
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
 
@@ -87,8 +88,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			.f1 = PCI_DEV(0, 0x18, 1),
 			.f2 = PCI_DEV(0, 0x18, 2),
 			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+			.channel0 = { DIMM0, DIMM2, 0, 0 },
+			.channel1 = { DIMM1, DIMM3, 0, 0 },
 		},
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 		{
@@ -97,8 +98,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			.f1 = PCI_DEV(0, 0x19, 1),
 			.f2 = PCI_DEV(0, 0x19, 2),
 			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+			.channel0 = { DIMM4, DIMM6, 0, 0 },
+			.channel1 = { DIMM5, DIMM7, 0, 0 },
 		},
 #endif
 	};
diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c
index 22ea09f436..1202001fdb 100644
--- a/src/mainboard/ibm/e326/romstage.c
+++ b/src/mainboard/ibm/e326/romstage.c
@@ -29,6 +29,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
 
 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include <spd.h>
 
 static void memreset_setup(void)
 {
@@ -87,8 +88,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			.f1 = PCI_DEV(0, 0x18, 1),
 			.f2 = PCI_DEV(0, 0x18, 2),
 			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+			.channel0 = { DIMM0, DIMM2, 0, 0 },
+			.channel1 = { DIMM1, DIMM3, 0, 0 },
 		},
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 		{
@@ -97,8 +98,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			.f1 = PCI_DEV(0, 0x19, 1),
 			.f2 = PCI_DEV(0, 0x19, 2),
 			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+			.channel0 = { DIMM4, DIMM6, 0, 0 },
+			.channel1 = { DIMM5, DIMM7, 0, 0 },
 		},
 #endif
 	};
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index 8412e33170..4a10c04afc 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -69,7 +69,7 @@ void main(unsigned long bist)
 	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
-		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 
 	SystemPreInit();
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 07ba0a0bdf..d70798c8a2 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -78,6 +78,7 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "lib/generic_sdram.c"
 #include "northbridge/intel/i3100/reset_test.c"
 #include "debug.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
 
@@ -136,8 +137,8 @@ void main(unsigned long bist)
 			.f1 = PCI_DEV(0, 0x00, 1),
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
-			.channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
-			.channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
+			.channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
+			.channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
 		}
 	};
 
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index 530c22ae24..22f5937e02 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -19,6 +19,7 @@
 #include "superio/nsc/pc87427/pc87427_early_init.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
@@ -41,10 +42,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void main(unsigned long bist)
 {
-	/*
-	 *
-	 *
-	 */
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
@@ -54,8 +51,8 @@ static void main(unsigned long bist)
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
 			*/
-			.channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 },
-			.channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 },
+			.channel0 = { DIMM2, DIMM1, DIMM0, 0 },
+			.channel1 = { DIMM6, DIMM5, DIMM4, 0 },
 		}
 	};
 
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index f36e4a4e68..5d34058a84 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -36,6 +36,7 @@
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "northbridge/intel/i3100/memory_initialized.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
@@ -64,8 +65,8 @@ void main(unsigned long bist)
 			.f1 = PCI_DEV(0, 0x00, 1),
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
-			.channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
-			.channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
+			.channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
+			.channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
 		}
 	};
 
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index 105b82115c..32cca1cfbf 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -61,7 +61,7 @@ static void main(unsigned long bist)
 		{
 			.node_id = 0,
 			.f0 = PCI_DEV(0, 0x00, 0),
-			.channel0 = { (0xa<<3)|2, (0xa<<3)|3 },
+			.channel0 = { DIMM2, DIMM3 },
 		}
 	};
 
diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c
index c04d63790c..4505cf2c91 100644
--- a/src/mainboard/intel/xe7501devkit/romstage.c
+++ b/src/mainboard/intel/xe7501devkit/romstage.c
@@ -16,9 +16,9 @@
 #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
-#define SUPERIO_PORT	0x2e
-#define SERIAL_DEV		PNP_DEV(SUPERIO_PORT, LPC47B272_SP1)
+#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
 
 static void hard_reset(void)
 {
@@ -41,8 +41,8 @@ static void main(unsigned long bist)
 		{
 			.d0 = PCI_DEV(0, 0, 0),
 			.d0f1 = PCI_DEV(0, 0, 1),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
-			.channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
+			.channel0 = { DIMM0, DIMM1, DIMM2, 0 },
+			.channel1 = { DIMM4, DIMM5, DIMM6, 0 },
 		},
 	};
 
diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c
index 0d70b70f82..0e1f078f82 100644
--- a/src/mainboard/jetway/j7f24/romstage.c
+++ b/src/mainboard/jetway/j7f24/romstage.c
@@ -34,6 +34,7 @@
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/fintek/f71805f/f71805f_early_serial.c"
 #include <lib.h>
+#include <spd.h>
 
 #if CONFIG_TTYS0_BASE == 0x2f8
 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2)
diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c
index fe4fd69327..d763a87bc7 100644
--- a/src/mainboard/lanner/em8510/romstage.c
+++ b/src/mainboard/lanner/em8510/romstage.c
@@ -27,6 +27,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
+#include <spd.h>
 #include "pc80/udelay_io.c"
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
@@ -54,7 +55,7 @@ void main(unsigned long bist)
 	static const struct mem_controller memctrl[] = {
 		{
 			.d0 = PCI_DEV(0, 0, 1),
-			.channel0 = { (0xa<<3)|0, 0 },
+			.channel0 = { DIMM0, 0 },
 		},
 	};
 
diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c
index 2b3ebe2d85..e317f041f4 100644
--- a/src/mainboard/lippert/frontrunner/romstage.c
+++ b/src/mainboard/lippert/frontrunner/romstage.c
@@ -11,7 +11,6 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5535/cs5535.h"
-#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -76,7 +75,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl [] = {
-		{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 	unsigned char temp;
 	SystemPreInit();
diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index bc6cae0053..35674fbfcc 100644
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -122,7 +122,7 @@ void main(unsigned long bist)
 	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
-		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 
 	SystemPreInit();
diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index 38bac67728..ca4980ba85 100644
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -34,7 +34,6 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -166,7 +165,7 @@ void main(unsigned long bist)
 	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
-		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 
 	SystemPreInit();
diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index 086a61d8f1..95a9c82b21 100644
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -97,7 +97,7 @@ void main(unsigned long bist)
 	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
-		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 
 	SystemPreInit();
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index cc9e7fda98..f5ae44e214 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -34,7 +34,6 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -163,7 +162,7 @@ void main(unsigned long bist)
 	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
-		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 
 	SystemPreInit();
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 2aa7740998..ca31857382 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -49,6 +49,7 @@
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
@@ -95,7 +96,7 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
-		(0xa << 3) | 0, (0xa << 3) | 1, 0, 0,
+		DIMM0, DIMM1, 0, 0,
 		0, 0, 0, 0,
 		0, 0, 0, 0,
 		0, 0, 0, 0,
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index b37cd1f4bf..13dd4049b4 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -42,6 +42,7 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <lib.h>
+#include <spd.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
@@ -117,11 +118,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
 		// Node 0
-		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
-		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
 		// Node 1
-		(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
-		(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+		DIMM4, DIMM6, 0, 0,
+		DIMM5, DIMM7, 0, 0,
 	};
 
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 74ec60af0a..5756b4c1c8 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -109,9 +109,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
-                       //first node
-                        RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
-                        RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
+                      //first node
+                       RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
+                       RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
                        //second node
                        RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
                        RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 6ec9daab18..e7754d0535 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -45,6 +45,7 @@
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
@@ -132,11 +133,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
 		// Node 0
-		RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
-		RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
+		RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
+		RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
 		// node 1
-		RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
-		RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
+		RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
+		RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 	};
 
 	unsigned bsp_apicid = 0;
diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c
index 84ece3897d..984aa9da54 100644
--- a/src/mainboard/newisys/khepri/romstage.c
+++ b/src/mainboard/newisys/khepri/romstage.c
@@ -14,6 +14,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -93,11 +94,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
-			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+			DIMM0, DIMM2, 0, 0,
+			DIMM1, DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+			DIMM4, DIMM6, 0, 0,
+			DIMM5, DIMM7, 0, 0,
 #endif
 	};
 
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 447d38d890..ed8e33a607 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -36,6 +36,7 @@
 #include <console/console.h>
 #include <usbdebug.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -132,11 +133,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
 			// Node 0
-			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+			DIMM0, DIMM2, 0, 0,
+			DIMM1, DIMM3, 0, 0,
 			// Node 1
-			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+			DIMM4, DIMM6, 0, 0,
+			DIMM5, DIMM7, 0, 0,
 	};
 
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index 5ccc348047..395e177800 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index 0312d4a27c..557d6329b3 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
index 32204b0238..1f567402d2 100644
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ b/src/mainboard/sunw/ultra40/romstage.c
@@ -8,6 +8,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -117,11 +118,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
 			// Node 0
-			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+			DIMM0, DIMM2, 0, 0,
+			DIMM1, DIMM3, 0, 0,
 			// Node 1
-			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+			DIMM4, DIMM6, 0, 0,
+			DIMM5, DIMM7, 0, 0,
 	};
 
         int needs_reset;
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 86705fdfb6..4f32816ebb 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -32,6 +32,7 @@
 
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -188,15 +189,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  */
 	static const uint16_t spd_addr[] = {
 		// Node 0
-		RC0 | (0xa << 3) | 0, RC0 | (0xa << 3) | 2,
-		    RC0 | (0xa << 3) | 4, RC0 | (0xa << 3) | 6,
-		RC0 | (0xa << 3) | 1, RC0 | (0xa << 3) | 3,
-		    RC0 | (0xa << 3) | 5, RC0 | (0xa << 3) | 7,
+		RC0 | DIMM0, RC0 | DIMM2,
+		RC0 | DIMM4, RC0 | DIMM6,
+		RC0 | DIMM1, RC0 | DIMM3,
+		RC0 | DIMM5, RC0 | DIMM7,
 		// Node 1
-		RC1 | (0xa << 3) | 0, RC1 | (0xa << 3) | 2,
-		    RC1 | (0xa << 3) | 4, RC1 | (0xa << 3) | 6,
-		RC1 | (0xa << 3) | 1, RC1 | (0xa << 3) | 3,
-		    RC1 | (0xa << 3) | 5, RC1 | (0xa << 3) | 7,
+		RC1 | DIMM0, RC1 | DIMM2,
+		RC1 | DIMM4, RC1 | DIMM6,
+		RC1 | DIMM1, RC1 | DIMM3,
+		RC1 | DIMM5, RC1 | DIMM7,
 	};
 
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index b84bdea2eb..eb5cc05c7a 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -35,6 +35,7 @@
 
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -124,11 +125,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
 			// Node 0
-			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+			DIMM0, DIMM2, 0, 0,
+			DIMM1, DIMM3, 0, 0,
 			// Node 1
-			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+			DIMM4, DIMM6, 0, 0,
+			DIMM5, DIMM7, 0, 0,
 	};
 
         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c
index 6a7d77b3bd..6f3c671dc3 100644
--- a/src/mainboard/supermicro/x6dai_g/romstage.c
+++ b/src/mainboard/supermicro/x6dai_g/romstage.c
@@ -20,6 +20,7 @@
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 #include "northbridge/intel/e7525/memory_initialized.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
@@ -44,10 +45,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void main(unsigned long bist)
 {
-	/*
-	 *
-	 *
-	 */
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
@@ -55,8 +52,8 @@ static void main(unsigned long bist)
 			.f1 = PCI_DEV(0, 0x00, 1),
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
-			.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
-			.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
+			.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
+			.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
 		}
 	};
 
diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c
index 64196b2fc5..18d8b265b2 100644
--- a/src/mainboard/supermicro/x6dhe_g/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g/romstage.c
@@ -21,6 +21,7 @@
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
@@ -58,8 +59,8 @@ static void main(unsigned long bist)
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
 			*/
-			.channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
-			.channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
+			.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
+			.channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
 		}
 	};
 
diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c
index 39cf5e778a..e8fcf306b7 100644
--- a/src/mainboard/supermicro/x6dhe_g2/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c
@@ -19,6 +19,7 @@
 #include "superio/nsc/pc87427/pc87427_early_init.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP2)
@@ -43,10 +44,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void main(unsigned long bist)
 {
-	/*
-	 *
-	 *
-	 */
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
@@ -56,8 +53,8 @@ static void main(unsigned long bist)
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
 			*/
-		    	.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
-			.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
+		    	.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
+			.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
 
 		}
 	};
diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c
index 4dc5efe94a..0a9af2d3bf 100644
--- a/src/mainboard/supermicro/x6dhr_ig/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c
@@ -19,6 +19,7 @@
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
@@ -57,8 +58,8 @@ static void main(unsigned long bist)
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
 			*/
-			.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
-			.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
+			.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
+			.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
 		}
 	};
 
diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
index 6d8e482463..efdacb5a5a 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
@@ -19,6 +19,7 @@
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
@@ -44,10 +45,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void main(unsigned long bist)
 {
-	/*
-	 *
-	 *
-	 */
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
@@ -57,8 +54,8 @@ static void main(unsigned long bist)
 			.f2 = PCI_DEV(0, 0x00, 2),
 			.f3 = PCI_DEV(0, 0x00, 3),
 			*/
-			.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
-			.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
+			.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
+			.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
 		}
 	};
 
diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
index b3aff80af4..7515a69136 100644
--- a/src/mainboard/traverse/geos/romstage.c
+++ b/src/mainboard/traverse/geos/romstage.c
@@ -63,7 +63,7 @@ void main(unsigned long bist)
 	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
-		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 
 	SystemPreInit();
diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c
index d117112c3d..8e765a173a 100644
--- a/src/mainboard/tyan/s2735/romstage.c
+++ b/src/mainboard/tyan/s2735/romstage.c
@@ -9,6 +9,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
@@ -44,8 +45,8 @@ void main(unsigned long bist)
                 {
                         .d0 = PCI_DEV(0, 0, 0),
                         .d0f1 = PCI_DEV(0, 0, 1),
-                        .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
-                        .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
+                        .channel0 = { DIMM0, DIMM1, DIMM2, 0 },
+                        .channel1 = { DIMM4, DIMM5, DIMM6, 0 },
                 },
 	};
 
diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c
index 5ae6c95d75..2711e2441e 100644
--- a/src/mainboard/tyan/s2850/romstage.c
+++ b/src/mainboard/tyan/s2850/romstage.c
@@ -9,6 +9,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -86,8 +87,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			.f1 = PCI_DEV(0, 0x18, 1),
 			.f2 = PCI_DEV(0, 0x18, 2),
 			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+			.channel0 = { DIMM0, DIMM2, 0, 0 },
+			.channel1 = { DIMM1, DIMM3, 0, 0 },
 		},
 	};
 
diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c
index 3d97099be5..728d2ecb72 100644
--- a/src/mainboard/tyan/s2875/romstage.c
+++ b/src/mainboard/tyan/s2875/romstage.c
@@ -9,6 +9,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -87,8 +88,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			.f1 = PCI_DEV(0, 0x18, 1),
 			.f2 = PCI_DEV(0, 0x18, 2),
 			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+			.channel0 = { DIMM0, DIMM2, 0, 0 },
+			.channel1 = { DIMM1, DIMM3, 0, 0 },
 		},
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 		{
@@ -97,8 +98,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			.f1 = PCI_DEV(0, 0x19, 1),
 			.f2 = PCI_DEV(0, 0x19, 2),
 			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+			.channel0 = { DIMM4, DIMM6, 0, 0 },
+			.channel1 = { DIMM5, DIMM7, 0, 0 },
 		},
 #endif
 	};
diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c
index e32f35a4eb..d3e8745355 100644
--- a/src/mainboard/tyan/s2880/romstage.c
+++ b/src/mainboard/tyan/s2880/romstage.c
@@ -9,6 +9,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -87,8 +88,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			.f1 = PCI_DEV(0, 0x18, 1),
 			.f2 = PCI_DEV(0, 0x18, 2),
 			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+			.channel0 = { DIMM0, DIMM2, 0, 0 },
+			.channel1 = { DIMM1, DIMM3, 0, 0 },
 		},
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 		{
@@ -97,8 +98,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			.f1 = PCI_DEV(0, 0x19, 1),
 			.f2 = PCI_DEV(0, 0x19, 2),
 			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+			.channel0 = { DIMM4, DIMM6, 0, 0 },
+			.channel1 = { DIMM5, DIMM7, 0, 0 },
 		},
 #endif
 	};
diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c
index ee3c3f0b69..c347e98cc9 100644
--- a/src/mainboard/tyan/s2881/romstage.c
+++ b/src/mainboard/tyan/s2881/romstage.c
@@ -8,6 +8,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -80,11 +81,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
-			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+			DIMM0, DIMM2, 0, 0,
+			DIMM1, DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+			DIMM4, DIMM6, 0, 0,
+			DIMM5, DIMM7, 0, 0,
 #endif
 	};
 
diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c
index c050c2bf49..c17bc1376c 100644
--- a/src/mainboard/tyan/s2882/romstage.c
+++ b/src/mainboard/tyan/s2882/romstage.c
@@ -9,6 +9,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -85,8 +86,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			.f1 = PCI_DEV(0, 0x18, 1),
 			.f2 = PCI_DEV(0, 0x18, 2),
 			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+			.channel0 = { DIMM0, DIMM2, 0, 0 },
+			.channel1 = { DIMM1, DIMM3, 0, 0 },
 		},
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 		{
@@ -95,8 +96,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			.f1 = PCI_DEV(0, 0x19, 1),
 			.f2 = PCI_DEV(0, 0x19, 2),
 			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+			.channel0 = { DIMM4, DIMM6, 0, 0 },
+			.channel1 = { DIMM5, DIMM7, 0, 0 },
 		},
 #endif
 	};
diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c
index deae2bbfdb..ab9b8d3077 100644
--- a/src/mainboard/tyan/s2885/romstage.c
+++ b/src/mainboard/tyan/s2885/romstage.c
@@ -8,6 +8,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -83,11 +84,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
-			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+			DIMM0, DIMM2, 0, 0,
+			DIMM1, DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+			DIMM4, DIMM6, 0, 0,
+			DIMM5, DIMM7, 0, 0,
 #endif
 	};
 
diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c
index 8c490a9006..973995e4af 100644
--- a/src/mainboard/tyan/s2891/romstage.c
+++ b/src/mainboard/tyan/s2891/romstage.c
@@ -8,6 +8,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -93,11 +94,11 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
-		(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-		(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-		(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-		(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+		DIMM4, DIMM6, 0, 0,
+		DIMM5, DIMM7, 0, 0,
 #endif
 	};
 
diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c
index 447fecfaaf..1cf18258e7 100644
--- a/src/mainboard/tyan/s2892/romstage.c
+++ b/src/mainboard/tyan/s2892/romstage.c
@@ -9,6 +9,7 @@
 
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 
@@ -88,11 +89,11 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
-		(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-		(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-		(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-		(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+		DIMM4, DIMM6, 0, 0,
+		DIMM5, DIMM7, 0, 0,
 #endif
 	};
 
diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c
index bb75a912cb..01e4280e24 100644
--- a/src/mainboard/tyan/s2895/romstage.c
+++ b/src/mainboard/tyan/s2895/romstage.c
@@ -8,6 +8,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
@@ -112,10 +113,10 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const u16 spd_addr [] = {
-		(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-		(0xa<<3)|1, (0xa<<3)|3, 0, 0,
-		(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-		(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+		DIMM0, DIMM2, 0, 0,
+		DIMM1, DIMM3, 0, 0,
+		DIMM4, DIMM6, 0, 0,
+		DIMM5, DIMM7, 0, 0,
 	};
 
 	int needs_reset;
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index efb9525488..745c00081a 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -35,6 +35,7 @@
 
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 #include <usbdebug.h>
 
 #include <cpu/amd/model_fxx_rev.h>
@@ -130,11 +131,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
 			// Node 0
-			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+			DIMM0, DIMM2, 0, 0,
+			DIMM1, DIMM3, 0, 0,
 			// Node 1
-			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+			DIMM4, DIMM6, 0, 0,
+			DIMM5, DIMM7, 0, 0,
 	};
 
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c
index 45df349cbc..5053924217 100644
--- a/src/mainboard/via/epia-cn/romstage.c
+++ b/src/mainboard/via/epia-cn/romstage.c
@@ -34,6 +34,7 @@
 #include "lib/delay.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "southbridge/via/vt8235/vt8235_early_serial.c"
+#include <spd.h>
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c
index 1b4e27a7af..a2ed0abdee 100644
--- a/src/mainboard/via/epia-n/romstage.c
+++ b/src/mainboard/via/epia-n/romstage.c
@@ -36,13 +36,10 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
 
-/*
- * NOOB ::
- * d0f0 - Device 0 Function 0 etc.
- */
 static const struct mem_controller ctrl = {
 	.d0f0 = 0x0000,
 	.d0f2 = 0x2000,
diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c
index 0b5a557125..a615c37cfd 100644
--- a/src/mainboard/via/pc2500e/romstage.c
+++ b/src/mainboard/via/pc2500e/romstage.c
@@ -34,6 +34,7 @@
 #include "lib/delay.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/ite/it8716f/it8716f_early_serial.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
 
diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c
index 8c761464f2..bd7426b1a8 100644
--- a/src/mainboard/via/vt8454c/romstage.c
+++ b/src/mainboard/via/vt8454c/romstage.c
@@ -39,6 +39,7 @@
 
 #include "northbridge/via/cx700/cx700_early_serial.c"
 #include "northbridge/via/cx700/raminit.c"
+#include <spd.h>
 
 static void enable_mainboard_devices(void)
 {
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index 6d081e9457..20dc587938 100644
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -67,7 +67,7 @@ void main(unsigned long bist)
 	post_code(0x01);
 
 	static const struct mem_controller memctrl[] = {
-		{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 
 	SystemPreInit();
diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index d272496462..9c0671e3b4 100644
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl [] = {
-		{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
+		{.channel0 = {DIMM0, DIMM1}}
 	};
 
 	SystemPreInit();