diff options
| author | Gabe Black <gabeblack@google.com> | 2012-03-30 14:33:02 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-01 20:01:18 +0200 |
| commit | 599e204efc5a55eb388a2ff11afb0e2196c21875 (patch) | |
| tree | 1ecb4dd00dcd6c44e5eb9f1ad4d6cb3b3aee042c /src | |
| parent | 8172d0be978d74eaaf103b592b505385db105f67 (diff) | |
Clean up Emerald Lake 2 mainboard directory
Change-Id: I4a64a56dda22050a31232807096e15565a665377
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/967
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/gpio.h | 6 | ||||
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/thermal.h | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/intel/emeraldlake2/gpio.h b/src/mainboard/intel/emeraldlake2/gpio.h index c458c839ab..05b9164fbf 100644 --- a/src/mainboard/intel/emeraldlake2/gpio.h +++ b/src/mainboard/intel/emeraldlake2/gpio.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef LINK_GPIO_H -#define LINK_GPIO_H +#ifndef EMERALDLAKE2_GPIO_H +#define EMERALDLAKE2_GPIO_H #include "southbridge/intel/bd82x6x/gpio.h" @@ -84,7 +84,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { const struct pch_gpio_set3 pch_gpio_set3_level = { }; -const struct pch_gpio_map link_gpio_map = { +const struct pch_gpio_map emeraldlake2_gpio_map = { .set1 = { .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 0cf113b9f3..879756bf71 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -242,7 +242,7 @@ void main(unsigned long bist) /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&link_gpio_map); + setup_pch_gpios(&emeraldlake2_gpio_map); setup_sio_gpios(); /* Early SuperIO setup */ diff --git a/src/mainboard/intel/emeraldlake2/thermal.h b/src/mainboard/intel/emeraldlake2/thermal.h index deb40c2b0f..883849dc38 100644 --- a/src/mainboard/intel/emeraldlake2/thermal.h +++ b/src/mainboard/intel/emeraldlake2/thermal.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef LINK_THERMAL_H -#define LINK_THERMAL_H +#ifndef EMERALDLAKE2_THERMAL_H +#define EMERALDLAKE2_THERMAL_H /* Fan is OFF */ #define FAN4_THRESHOLD_OFF 0 |