mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup

Support SAMSUNG KMDP6001DA-B425 and MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR

From the calibration log of MICRON MT29VZZZAD8DQKSL, we found
the begin pass range of RX window earlier than with other DDR type.
So need change the DQS starting offset to increase the scan range of RX window.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on EMCP DRAM

Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com>

5 files changed, 87 insertions, 1 deletions

diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c
index cbfb08d5ce..5931c79ecd 100644
--- a/src/mainboard/google/kukui/sdram_configs.c
+++ b/src/mainboard/google/kukui/sdram_configs.c
@@ -21,6 +21,8 @@
 static const char *const sdram_configs[] = {
 	[1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB",
 	[2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB",
+	[3] = "sdram-lpddr4x-KMDP6001DA-B425-4GB",
+	[5] = "sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB",
 };
 
 static struct sdram_params params;
diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc
index 1e11140873..77158a5c59 100644
--- a/src/mainboard/google/kukui/sdram_params/Makefile.inc
+++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc
@@ -1,6 +1,8 @@
 sdram-params :=
 sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB
 sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB
+sdram-params += sdram-lpddr4x-KMDP6001DA-B425-4GB
+sdram-params += sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB
 
 $(foreach params,$(sdram-params), \
 	$(eval cbfs-files-y += $(params)) \
diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c
new file mode 100644
index 0000000000..1e0c3628fd
--- /dev/null
+++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/emi.h>
+
+struct sdram_params params = {
+	.impedance = {
+		[ODT_OFF] = {0x9, 0x7, 0x0, 0xF},
+		[ODT_ON] = {0xA, 0x9, 0x0, 0xE}
+	},
+	.wr_level = {
+		[CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} },
+		[CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} }
+	},
+	.cbt_cs = {
+		[CHANNEL_A] = {0x1, 0x1},
+		[CHANNEL_B] = {0x2, 0x2}
+	},
+	.cbt_mr12 = {
+		[CHANNEL_A] = {0x56, 0x56},
+		[CHANNEL_B] = {0x58, 0x5C}
+	},
+	.emi_cona_val = 0xF053F154,
+	.emi_conh_val = 0x44440003,
+	.emi_conf_val = 0x00421000,
+	.chn_emi_cona_val = {0x0444F051, 0x0444F051},
+	.cbt_mode_extern = CBT_NORMAL_MODE,
+	.delay_cell_unit = 868,
+};
diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c
new file mode 100644
index 0000000000..512023b35e
--- /dev/null
+++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/emi.h>
+
+struct sdram_params params = {
+	.impedance = {
+		[ODT_OFF] = {0x9, 0x7, 0x0, 0xF},
+		[ODT_ON] = {0xA, 0x9, 0x0, 0xE}
+	},
+	.wr_level = {
+		[CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} },
+		[CHANNEL_B] = { {0x21, 0x28}, {0x21, 0x29} }
+	},
+	.cbt_cs = {
+		[CHANNEL_A] = {0x2, 0x2},
+		[CHANNEL_B] = {0x2, 0x2}
+	},
+	.cbt_mr12 = {
+		[CHANNEL_A] = {0x5E, 0x5E},
+		[CHANNEL_B] = {0x5E, 0x5C}
+	},
+	.emi_cona_val = 0xF053F154,
+	.emi_conh_val = 0x44440003,
+	.emi_conf_val = 0x00421000,
+	.chn_emi_cona_val = {0x0444F051, 0x0444F051},
+	.cbt_mode_extern = CBT_NORMAL_MODE,
+	.delay_cell_unit = 868,
+};
diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
index 6dc8fa6588..05f793ec4b 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
@@ -32,7 +32,7 @@ enum {
 
 enum {
 	FIRST_DQ_DELAY = 0,
-	FIRST_DQS_DELAY = -10,
+	FIRST_DQS_DELAY = -16,
 	MAX_DQDLY_TAPS = 16,
 	MAX_RX_DQDLY_TAPS = 63,
 };