diff options
| author | Matt Delco <delco@chromium.org> | 2018-08-15 11:51:43 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-20 15:54:13 +0000 |
| commit | 1950ed9ee3baaf3ecfd3fb2583bfdce562395cb7 (patch) | |
| tree | eeeecffacd5728855d2c4153dd79fa71e82e3375 /src | |
| parent | 9084c3c31bf62bc5c38cf5a1edbd830e407675c6 (diff) | |
mb/google/eve: enable eist
Enable Enhanced Intel SpeedStep (EIST) on eve.
Change-Id: I49b18b817cda570f5c3c4d048c4e03329ac10b87
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/eve/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 16bfc47a59..c1482c6296 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -7,6 +7,8 @@ chip soc/intel/skylake register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" + register "eist_enable" = "1" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE |