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authorSubrata Banik <subrata.banik@intel.com>2017-08-16 18:58:21 +0530
committerAaron Durbin <adurbin@chromium.org>2017-08-25 18:07:01 +0000
commit15943df29c31d581a160612ef1757e7d24729dd7 (patch)
tree2804b3f3f8f5dedf6805e15b1e49ae0dbd433d83 /src
parent4f6e341e88e94e81087a1538b3364dcd47641c7f (diff)
soc/intel/skylake: Remove TCO lock down programming
FSP is doing TCO lock inside Post PCI bus enumeration NotifyPhase(). Hence remove TCO Lock down programming from coreboot. TEST= Ensure TCO_LOCK offset 8 bit 12 is set. Change-Id: Iec9e3075df01862f8558b303a458126c68202bff Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/finalize.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index c79f2acfbd..c38ac632c5 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -107,8 +107,6 @@ static void pch_finalize_script(void)
{
device_t dev;
uint32_t reg32;
- u16 tcobase;
- u16 tcocnt;
uint8_t *pmcbase;
config_t *config;
u8 reg8;
@@ -119,12 +117,6 @@ static void pch_finalize_script(void)
/* Lock FAST_SPIBAR */
fast_spi_lock_bar();
- /* TCO Lock down */
- tcobase = smbus_tco_regs();
- tcocnt = inw(tcobase + TCO1_CNT);
- tcocnt |= TCO_LOCK;
- outw(tcocnt, tcobase + TCO1_CNT);
-
/* Display me status before we hide it */
intel_me_status();