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authorElyes HAOUAS <ehaouas@noos.fr>2018-01-28 22:35:47 +0100
committerFelix Held <felix-coreboot@felixheld.de>2018-04-29 17:09:09 +0000
commit12d65f80dae1de18b9600a0bce87286312457b61 (patch)
treec02883e590a677e50d2e386dbc3edc9eb84117f7 /src
parent47d587c837ebe39d6c6e8bf18eaf1401c1126a6e (diff)
amd/agesa/family14,15 & 16: Remove unnecessary whitespace
Change-Id: I9495b47a85a6fb9d8d06d9a82c0444b794ec4933 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/amd/agesa/family14/model_14_init.c2
-rw-r--r--src/cpu/amd/agesa/family15tn/model_15_init.c2
-rw-r--r--src/cpu/amd/agesa/family16kb/model_16_init.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index a03516daaf..2f7abd89c0 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -42,7 +42,7 @@ static void model_14_init(device_t dev)
#endif
printk(BIOS_DEBUG, "Model 14 Init.\n");
- disable_cache ();
+ disable_cache();
/*
* AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
* by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14.
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index e0bff4f4e3..5f2c60343e 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -46,7 +46,7 @@ static void model_15_init(device_t dev)
//x86_enable_cache();
//amd_setup_mtrrs();
//x86_mtrr_check();
- disable_cache ();
+ disable_cache();
/* Enable access to AMD RdDram and WrDram extension bits */
msr = rdmsr(SYSCFG_MSR);
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index d49216a734..aa568812b7 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -44,7 +44,7 @@ static void model_16_init(device_t dev)
//x86_enable_cache();
//amd_setup_mtrrs();
//x86_mtrr_check();
- disable_cache ();
+ disable_cache();
/* Enable access to AMD RdDram and WrDram extension bits */
msr = rdmsr(SYSCFG_MSR);
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;